mirror of https://github.com/hsoft/collapseos.git
346 lines
7.5 KiB
NASM
346 lines
7.5 KiB
NASM
.include "tn45def.inc"
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; Receives keystrokes from PS/2 keyboard and send them to the '164. On the PS/2
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; side, it works the same way as the controller in the rc2014/ps2 recipe.
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; However, in this case, what we have on the other side isn't a z80 bus, it's
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; the one of the two controller ports of the SMS through a DB9 connector.
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; The PS/2 related code is copied from rc2014/ps2 without much change. The only
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; differences are that it pushes its data to a '164 instead of a '595 and that
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; it synchronizes with the SMS with a SR latch, so we don't need PCINT. We can
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; also afford to run at 1MHz instead of 8.
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; *** Register Usage ***
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;
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; GPIOR0 flags:
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; 0 - when set, indicates that the DATA pin was high when we received a
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; bit through INT0. When we receive a bit, we set flag T to indicate
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; it.
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;
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; R16: tmp stuff
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; R17: recv buffer. Whenever we receive a bit, we push it in there.
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; R18: recv step:
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; - 0: idle
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; - 1: receiving data
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; - 2: awaiting parity bit
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; - 3: awaiting stop bit
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; R19: Register used for parity computations and tmp value in some other places
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; R20: data being sent to the '164
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; Y: pointer to the memory location where the next scan code from ps/2 will be
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; written.
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; Z: pointer to the next scan code to push to the 595
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;
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; *** Constants ***
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.equ CLK = PINB2
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.equ DATA = PINB1
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.equ CP = PINB3
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; SR-Latch's Q pin
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.equ LQ = PINB0
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; SR-Latch's R pin
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.equ LR = PINB4
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; init value for TCNT0 so that overflow occurs in 100us
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.equ TIMER_INITVAL = 0x100-100
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; *** Code ***
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rjmp main
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rjmp hdlINT0
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; Read DATA and set GPIOR0/0 if high. Then, set flag T.
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; no SREG fiddling because no SREG-modifying instruction
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hdlINT0:
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sbic PINB, DATA ; DATA clear? skip next
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sbi GPIOR0, 0
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set
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reti
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main:
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ldi r16, low(RAMEND)
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out SPL, r16
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ldi r16, high(RAMEND)
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out SPH, r16
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; init variables
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clr r18
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out GPIOR0, r18
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; Setup int0
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; INT0, falling edge
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ldi r16, (1<<ISC01)
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out MCUCR, r16
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; Enable INT0
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ldi r16, (1<<INT0)
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out GIMSK, r16
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; Setup buffer
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clr YH
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ldi YL, low(SRAM_START)
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clr ZH
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ldi ZL, low(SRAM_START)
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; Setup timer. We use the timer to clear up "processbit" registers after
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; 100us without a clock. This allows us to start the next frame in a
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; fresh state. at 1MHZ, no prescaling is necessary. Each TCNT0 tick is
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; already 1us long.
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ldi r16, (1<<CS00) ; no prescaler
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out TCCR0B, r16
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; init DDRB
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sbi DDRB, CP
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cbi PORTB, LR
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sbi DDRB, LR
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sei
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loop:
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brts processbit ; flag T set? we have a bit to process
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cp YL, ZL ; if YL == ZL, buffer is empty
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brne sendTo164 ; YL != ZL? our buffer has data
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; nothing to do. Before looping, let's check if our communication timer
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; overflowed.
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in r16, TIFR
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sbrc r16, TOV0
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rjmp processbitReset ; Timer0 overflow? reset processbit
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; Nothing to do for real.
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rjmp loop
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; Process the data bit received in INT0 handler.
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processbit:
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in r19, GPIOR0 ; backup GPIOR0 before we reset T
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andi r19, 0x1 ; only keep the first flag
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cbi GPIOR0, 0
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clt ; ready to receive another bit
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; We've received a bit. reset timer
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rcall resetTimer
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; Which step are we at?
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tst r18
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breq processbits0
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cpi r18, 1
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breq processbits1
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cpi r18, 2
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breq processbits2
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; step 3: stop bit
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clr r18 ; happens in all cases
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; DATA has to be set
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tst r19 ; Was DATA set?
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breq loop ; not set? error, don't push to buffer
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; push r17 to the buffer
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st Y+, r17
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rcall checkBoundsY
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rjmp loop
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processbits0:
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; step 0 - start bit
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; DATA has to be cleared
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tst r19 ; Was DATA set?
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brne loop ; Set? error. no need to do anything. keep r18
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; as-is.
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; DATA is cleared. prepare r17 and r18 for step 1
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inc r18
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ldi r17, 0x80
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rjmp loop
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processbits1:
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; step 1 - receive bit
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; We're about to rotate the carry flag into r17. Let's set it first
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; depending on whether DATA is set.
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clc
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sbrc r19, 0 ; skip if DATA cleared.
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sec
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; Carry flag is set
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ror r17
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; Good. now, are we finished rotating? If carry flag is set, it means
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; that we've rotated in 8 bits.
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brcc loop ; we haven't finished yet
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; We're finished, go to step 2
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inc r18
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rjmp loop
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processbits2:
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; step 2 - parity bit
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mov r1, r19
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mov r19, r17
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rcall checkParity ; --> r16
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cp r1, r16
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brne processbitError ; r1 != r16? wrong parity
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inc r18
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rjmp loop
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processbitError:
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clr r18
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ldi r19, 0xfe
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rcall sendToPS2
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rjmp loop
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processbitReset:
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clr r18
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rcall resetTimer
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rjmp loop
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; Send the value of r20 to the '164
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sendTo164:
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sbis PINB, LQ ; LQ is set? we can send the next byte
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rjmp loop ; Even if we have something in the buffer, we
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; can't: the SMS hasn't read our previous
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; buffer yet.
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; We disable any interrupt handling during this routine. Whatever it
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; is, it has no meaning to us at this point in time and processing it
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; might mess things up.
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cli
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sbi DDRB, DATA
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ld r20, Z+
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rcall checkBoundsZ
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ldi r16, 8
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sendTo164Loop:
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cbi PORTB, DATA
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sbrc r20, 7 ; if leftmost bit isn't cleared, set DATA high
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sbi PORTB, DATA
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; toggle CP
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cbi PORTB, CP
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lsl r20
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sbi PORTB, CP
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dec r16
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brne sendTo164Loop ; not zero yet? loop
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; release PS/2
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cbi DDRB, DATA
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sei
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; Reset the latch to indicate that the next number is ready
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sbi PORTB, LR
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cbi PORTB, LR
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rjmp loop
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resetTimer:
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ldi r16, TIMER_INITVAL
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out TCNT0, r16
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ldi r16, (1<<TOV0)
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out TIFR, r16
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ret
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; Send the value of r19 to the PS/2 keyboard
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sendToPS2:
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cli
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; First, indicate our request to send by holding both Clock low for
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; 100us, then pull Data low
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; lines low for 100us.
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cbi PORTB, CLK
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sbi DDRB, CLK
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rcall resetTimer
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; Wait until the timer overflows
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in r16, TIFR
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sbrs r16, TOV0
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rjmp PC-2
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; Good, 100us passed.
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; Pull Data low, that's our start bit.
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cbi PORTB, DATA
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sbi DDRB, DATA
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; Now, let's release the clock. At the next raising edge, we'll be
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; expected to have set up our first bit (LSB). We set up when CLK is
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; low.
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cbi DDRB, CLK ; Should be starting high now.
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; We will do the next loop 8 times
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ldi r16, 8
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; Let's remember initial r19 for parity
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mov r1, r19
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sendToPS2Loop:
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; set up DATA
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cbi PORTB, DATA
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sbrc r19, 0 ; skip if LSB is clear
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sbi PORTB, DATA
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lsr r19
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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dec r16
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brne sendToPS2Loop ; not zero? loop
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; Data was sent, CLK is high. Let's send parity
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mov r19, r1 ; recall saved value
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rcall checkParity ; --> r16
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; set parity bit
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cbi PORTB, DATA
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sbrc r16, 0 ; parity bit in r16
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sbi PORTB, DATA
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; We can now release the DATA line
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cbi DDRB, DATA
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; Wait for DATA to go low. That's our ACK
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sbic PINB, DATA
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rjmp PC-1
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; We're finished! Enable INT0, reset timer, everything back to normal!
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rcall resetTimer
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clt ; also, make sure T isn't mistakely set.
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sei
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ret
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; Check that Y is within bounds, reset to SRAM_START if not.
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checkBoundsY:
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tst YL
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breq PC+2
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ret ; not zero, nothing to do
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; YL is zero. Reset Y
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clr YH
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ldi YL, low(SRAM_START)
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ret
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; Check that Z is within bounds, reset to SRAM_START if not.
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checkBoundsZ:
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tst ZL
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breq PC+2
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ret ; not zero, nothing to do
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; ZL is zero. Reset Z
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clr ZH
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ldi ZL, low(SRAM_START)
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ret
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; Counts the number of 1s in r19 and set r16 to 1 if there's an even number of
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; 1s, 0 if they're odd.
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checkParity:
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ldi r16, 1
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lsr r19
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brcc PC+2 ; Carry unset? skip next
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inc r16 ; Carry set? We had a 1
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tst r19 ; is r19 zero yet?
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brne checkParity+1 ; no? loop and skip first LDI
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andi r16, 0x1 ; Sets Z accordingly
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ret
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