mirror of https://github.com/hsoft/collapseos.git
recipes/sms/kbd: PS/2 keyboard adapter for the SMS!
This commit is contained in:
Virgil Dupras
parent
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README.md
38
README.md
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@ -6,14 +6,12 @@ Collapse OS is a z80 kernel and a collection of programs, tools and
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documentation that allows you to assemble an OS that, when completed, will be
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able to:
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1. Run on an extremely minimal and improvised architecture.
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2. Communicate through a improvised serial interface linked to some kind of
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improvised terminal.
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1. Run on minimal and improvised machines.
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2. Interface through improvised means (serial, keyboard, display).
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3. Edit text files.
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4. Compile assembler source files for a wide range of MCUs and CPUs.
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5. Write files to a wide range of flash ICs and MCUs.
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6. Access data storage from improvised systems.
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7. Replicate itself.
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5. Read and write from a wide range of storage devices.
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6. Replicate itself.
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Additionally, the goal of this project is to be as self-contained as possible.
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With a copy of this project, a capable and creative person should be able to
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@ -21,27 +19,6 @@ manage to build and install Collapse OS without external resources (i.e.
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internet) on a machine of her design, built from scavenged parts with low-tech
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tools.
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## Status
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The project unfinished but is progressing well! Highlights:
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* Self replicates: Can assemble itself from within itself, given enough RAM and
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storage.
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* Has a shell that can poke memory, I/O, call arbitrary code from memory.
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* Can "upload" code from serial link into memory and execute it.
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* Can manage multiple "block devices".
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* Can read and write to SD cards.
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* A z80 assembler, written in z80 that is self-assembling and can assemble the
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whole project.
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* Compact:
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* Kernel: 3K binary, 1800 SLOC.
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* ZASM: 4K binary, 2300 SLOC, 16K RAM usage to assemble kernel or itself.
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* Extremely flexible: Kernel parts are written as loosely knit modules that
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are bound through glue code. This makes the kernel adaptable to many unforseen
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situations.
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* From a GNU environment, can be built with minimal tooling: only
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[libz80][libz80], make and a C compiler are needed.
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## Organisation of this repository
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* `kernel`: Pieces of code to be assembled by the user into a kernel.
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@ -55,9 +32,10 @@ The project unfinished but is progressing well! Highlights:
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Each folder has a README with more details.
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## More information
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## Status
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Go to [Collapse OS' website](https://collapseos.org) for more information on the
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project.
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The project unfinished but is progressing well! See [Collapse OS' website][web]
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for more information.
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[libz80]: https://github.com/ggambetta/libz80
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[web]: https://collapseos.org
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@ -1,13 +1,17 @@
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; kbd - implement GetC for PS/2 keyboard
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;
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; Status: Work in progress. See recipes/rc2014/ps2
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; It reads raw key codes from a FetchKC routine and returns, if appropriate,
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; a proper ASCII char to type. See recipes rc2014/ps2 and sms/kbd.
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;
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; *** Defines ***
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; The port of the device where we read scan codes. See recipe rc2014/ps2.
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; KBD_PORT
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; Pointer to a routine that fetches the last typed keyword in A. Should return
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; 0 when nothing was typed.
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; KBD_FETCHKC
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; *** Variables ***
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.equ KBD_SKIP_NEXT KBD_RAMSTART
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; Pointer to a routine that fetches the last typed keyword in A. Should return
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; 0 when nothing was typed.
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.equ KBD_RAMEND KBD_SKIP_NEXT+1
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kbdInit:
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@ -16,7 +20,7 @@ kbdInit:
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ret
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kbdGetC:
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in a, (KBD_PORT)
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call KBD_FETCHKC
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or a
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jr z, .nothing
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@ -0,0 +1,102 @@
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; kbd - implement FetchKC for SMS PS/2 adapter
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;
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; Implements KBD_FETCHKC for the adapter described in recipe sms/kbd. It does
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; so for both Port A and Port B (you hook whichever you prefer).
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; FetchKC on Port A
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smskbdFetchKCA:
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; Before reading a character, we must first verify that there is
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; something to read. When the adapter is finished filling its '164 up,
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; it resets the latch, which output's is connected to TL. When the '164
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; is full, TL is low.
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; Port A TL is bit 4
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in a, (0xdc)
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and 0b00010000
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jr nz, .nothing
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push bc
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in a, (0x3f)
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; Port A TH output, low
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ld a, 0b11011101
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out (0x3f), a
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nop
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nop
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in a, (0xdc)
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; bit 3:0 are our dest bits 3:0. handy...
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and 0b00001111
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ld b, a
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; Port A TH output, high
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ld a, 0b11111101
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out (0x3f), a
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nop
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nop
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in a, (0xdc)
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; bit 3:0 are our dest bits 7:4
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rlca \ rlca \ rlca \ rlca
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and 0b11110000
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or b
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ex af, af'
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; Port A/B reset
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ld a, 0xff
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out (0x3f), a
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ex af, af'
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pop bc
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ret
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.nothing:
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xor a
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ret
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; FetchKC on Port B
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smskbdFetchKCB:
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; Port B TL is bit 2
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in a, (0xdd)
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and 0b00000100
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jr nz, .nothing
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push bc
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in a, (0x3f)
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; Port B TH output, low
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ld a, 0b01110111
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out (0x3f), a
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nop
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nop
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in a, (0xdc)
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; bit 7:6 are our dest bits 1:0
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rlca \ rlca
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and 0b00000011
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ld b, a
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in a, (0xdd)
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; bit 1:0 are our dest bits 3:2
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rlca \ rlca
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and 0b00001100
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or b
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ld b, a
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; Port B TH output, high
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ld a, 0b11110111
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out (0x3f), a
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nop
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nop
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in a, (0xdc)
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; bit 7:6 are our dest bits 5:4
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rrca \ rrca
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and 0b00110000
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or b
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ld b, a
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in a, (0xdd)
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; bit 1:0 are our dest bits 7:6
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rrca \ rrca
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and 0b11000000
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or b
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ex af, af'
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; Port A/B reset
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ld a, 0xff
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out (0x3f), a
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ex af, af'
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pop bc
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ret
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.nothing:
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xor a
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ret
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@ -26,6 +26,7 @@ are other recipes related to the RC2014:
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* [Writing to a AT28 from Collapse OS](eeprom/README.md)
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* [Accessing a MicroSD card](sdcard/README.md)
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* [Assembling binaries](zasm/README.md)
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* [Interfacing a PS/2 keyboard](ps2/README.md)
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## Goal
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@ -35,3 +35,8 @@ init:
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call stdioInit
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call shellInit
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jp shellLoop
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KBD_FETCHKC:
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in a, (KBD_PORT)
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ret
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@ -74,7 +74,6 @@
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; - 1: receiving data
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; - 2: awaiting parity bit
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; - 3: awaiting stop bit
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; it reaches 11, we know we're finished with the frame.
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; R19: Register used for parity computations and tmp value in some other places
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; R20: data being sent to the 595
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; Y: pointer to the memory location where the next scan code from ps/2 will be
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@ -167,9 +166,14 @@ loop:
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brts processbit ; flag T set? we have a bit to process
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cp YL, ZL ; if YL == ZL, buffer is empty
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brne sendTo595 ; YL != ZL? our buffer has data
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; nothing to do. Before looping, let's check if our communication timer
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; overflowed.
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in r16, TIFR
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sbrc r16, TOV0
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rjmp processbitReset ; Timer0 overflow? reset processbit
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; Nothing to do for real.
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rjmp loop
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; Process the data bit received in INT0 handler.
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@ -12,6 +12,13 @@ platform and this is where most of my information comes from.
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This platform is tight on RAM. It has 8k of it. However, if you have extra RAM,
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you can put it on your cartridge.
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## Related recipes
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This recipe is for installing a minimal Collapse OS system on the SMS. There
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are other recipes related to the SMS:
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* [Interfacing a PS/2 keyboard](kbd/README.md)
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## Gathering parts
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* [zasm][zasm]
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@ -47,7 +54,8 @@ D-Pad is used as follow:
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* Start button is like pressing Return.
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Of course, that's not a fun way to enter text, but using the D-Pad is the
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easiest way to get started. I'm working on a PS/2 keyboard adapter for the SMS.
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easiest way to get started which doesn't require soldering. Your next step after
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that would be to [build a PS/2 keyboard adapter!](kbd/README.md)
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[smspower]: http://www.smspower.org
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[everdrive]: https://krikzz.com
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@ -0,0 +1,25 @@
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PROGNAME = ps2ctl
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AVRDUDEMCU ?= t45
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AVRDUDEARGS ?= -c usbtiny -P usb
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TARGETS = $(PROGNAME).hex os.sms
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ZASM = ../../../tools/zasm.sh
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KERNEL = ../../../kernel
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# Rules
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.PHONY: send all clean
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all: $(TARGETS)
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@echo Done!
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send: $(PROGNAME).hex
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avrdude $(AVRDUDEARGS) -p $(AVRDUDEMCU) -U flash:w:$<
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$(PROGNAME).hex: $(PROGNAME).asm
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avra -o $@ $<
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os.sms: glue.asm
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$(ZASM) $(KERNEL) < $< > $@
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clean:
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rm -f $(TARGETS) *.eep.hex *.obj os.bin
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@ -0,0 +1,117 @@
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# PS/2 keyboard on the SMS
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Using the shell with a D-pad on the SMS is doable, but not fun at all! We're
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going to build an adapter for a PS/2 keyboard to plug as a SMS controller.
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The PS/2 logic will be the same as the [RC2014's PS/2 adapter][rc2014-ps2] but
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instead of interfacing directly with the bus, we interface with the SMS'
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controller subsystem (that is, what we poke on ports `0x3f` and `0xdc`).
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How will we achieve that? A naive approach would be "let's limit ourselves to
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7bit ASCII and put `TH`, `TR` and `TL` as inputs". That could work, except that
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the SMS will have no way reliable way (except timers) of knowing whether polling
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two identical values is the result of a repeat character or because there is no
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new value yet.
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On the AVR side, there's not way to know whether the value has been read, so we
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can't to like on the RC2014 and reset the value to zero when a `RO` request is
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made.
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We need communication between the SMS and the PS/2 adapter to be bi-directional.
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That bring the number of usable pins down to 6, a bit low for a proper character
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range. So we'll fetch each character in two 4bit nibbles. `TH` is used to select
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which nibble we want.
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`TH` going up also tells the AVR MCU that we're done reading the character and
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that the next one can come up.
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As always, the main problem is that the AVR MCU is too slow to keep up with the
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rapid z80 polling pace. In the RC2014 adapter, I hooked `CE` directly on the
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AVR, but that was a bit tight because the MCU is barely fast enough to handle
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this signal properly. I did that because I had no proper IC on hand to build a
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SR latch.
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In this recipe, I do have a SR latch on hand, so I'll use it. `TH` triggering
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will also trigger that latch, indicating to the MCU that it can load the next
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character in the '164. When it's done, we signal the SMS that the next char is
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ready by reseting the latch. That means that we have to hook the latch's output
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to `TR`.
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Nibble selection on `TH` doesn't involve the AVR at all. All 8 bits are
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pre-loaded on the '164. We use a 4-channel multiplexer to make `TH` select
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either the low or high bits.
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## Gathering parts
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* A SMS that can run Collapse OS
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* A PS/2 keyboard. A USB keyboard + PS/2 adapter should work, but I haven't
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tried it yet.
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* A PS/2 female connector. Not so readily available, at least not on digikey. I
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de-soldered mine from an old motherboard I had laying around.
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* A SMS controller you can cannibalize for the DB-9 connection. A stock DB-9
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connector isn't deep enough.
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* ATtiny85/45/25 (main MCU for the device)
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* 74xx164 (shift register)
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* 74xx157 (multiplexer)
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* A NOR SR-latch. I used a 4043.
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* Proto board, wires, IC sockets, etc.
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* [AVRA][avra]
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## Historical note
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As I was building this prototype, I was wondering how I would debug it. I could
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obviously not hope for it to work as a keyboard adapter on the first time, right
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on port A, driving the shell. I braced myself mentally for a logic analyzer
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session and some kind of arduino-based probe to test bit banging results.
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And then I thought "why not use the genesis?". Sure, driving the shell with the
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D-pad isn't fun at all, but it's possible. So I hacked myself a temporary debug
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kernel with a "a" command doing a probe on port B. It worked really well!
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It was a bit less precise than logic analyzers and a bit of poking-around and
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crossing-fingers was involved, but overall, I think it was much less effort
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than creating a full test setup.
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There's a certain satisfaction to debug a device entirely on your target
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machine...
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## Building the PS/2 interface
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(schematic incoming, I have yet to scan it.)
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The PS/2-to-AVR part is indentical to the rc2014/ps2 recipe. Refer to this
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recipe.
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We control the '164 from the AVR in a similar way to what we did in rc2014/ps2,
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that is, sharing the DATA line with PS/2 (PB1). We clock the '164 with PB3.
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Because the '164, unlike the '595, is unbuffered, no need for special RCLK
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provisions.
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Most of the wiring is between the '164 and the '157. Place them close. The 4
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outputs on the '157 are hooked to the first 4 lines on the DB-9 (Up, Down, Left,
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Right).
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In my prototype, I placed a 1uf decoupling cap next to the AVR. I used a 10K
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resistor as a pull-down for the TH line (it's not always driven).
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If you use a 4043, don't forget to wire EN. On the '157, don't forget to wire
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~G.
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The code expects a SR-latch that works like a 4043, that is, S and R are
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triggered high, S makes Q high, R makes Q low. R is hooked to PB4. S is hooked
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to TH (and also the A/B on the '157). Q is hooked to PB0 and TL.
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## Usage
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The code in this recipe is set up to listen to the keyboard on port B, leaving
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port A to drive, for example, an Everdrive with a D-pad. Unlike the generic
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SMS recipe, this kernel has no character selection mechanism. It acts like a
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regular shell, taking input from the keyboard.
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`kernel/sms/kbd.asm` also has a FetchKC implementation for port A if you prefer.
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Just hook it on. I've tried it, it works.
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Did you get there? Feels pretty cool huh?
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[rc2014-ps2]: ../../rc2014/ps2
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[avra]: https://github.com/hsoft/avra
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@ -0,0 +1,57 @@
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; 8K of onboard RAM
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.equ RAMSTART 0xc000
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; Memory register at the end of RAM. Must not overwrite
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.equ RAMEND 0xfdd0
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jp init
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.fill 0x66-$
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retn
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#include "err.h"
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#include "core.asm"
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#include "parse.asm"
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#include "sms/kbd.asm"
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.equ KBD_RAMSTART RAMSTART
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.equ KBD_FETCHKC smskbdFetchKCA
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#include "kbd.asm"
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.equ VDP_RAMSTART KBD_RAMEND
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#include "sms/vdp.asm"
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.equ STDIO_RAMSTART VDP_RAMEND
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#include "stdio.asm"
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.equ SHELL_RAMSTART STDIO_RAMEND
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.equ SHELL_EXTRA_CMD_COUNT 0
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#include "shell.asm"
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init:
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di
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im 1
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ld sp, RAMEND
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; Initialize the keyboard latch by "dummy reading" once. This ensures
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; that the adapter knows it can fill its '164.
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; Port B TH output, high
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ld a, 0b11110111
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out (0x3f), a
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nop
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; Port A/B reset
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ld a, 0xff
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out (0x3f), a
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call kbdInit
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call vdpInit
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ld hl, kbdGetC
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ld de, vdpPutC
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call stdioInit
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call shellInit
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jp shellLoop
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.fill 0x7ff0-$
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.db "TMR SEGA", 0x00, 0x00, 0xfb, 0x68, 0x00, 0x00, 0x00, 0x4c
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|
|
@ -0,0 +1,345 @@
|
|||
.include "tn45def.inc"
|
||||
|
||||
; Receives keystrokes from PS/2 keyboard and send them to the '164. On the PS/2
|
||||
; side, it works the same way as the controller in the rc2014/ps2 recipe.
|
||||
; However, in this case, what we have on the other side isn't a z80 bus, it's
|
||||
; the one of the two controller ports of the SMS through a DB9 connector.
|
||||
|
||||
; The PS/2 related code is copied from rc2014/ps2 without much change. The only
|
||||
; differences are that it pushes its data to a '164 instead of a '595 and that
|
||||
; it synchronizes with the SMS with a SR latch, so we don't need PCINT. We can
|
||||
; also afford to run at 1MHz instead of 8.
|
||||
|
||||
; *** Register Usage ***
|
||||
;
|
||||
; GPIOR0 flags:
|
||||
; 0 - when set, indicates that the DATA pin was high when we received a
|
||||
; bit through INT0. When we receive a bit, we set flag T to indicate
|
||||
; it.
|
||||
;
|
||||
; R16: tmp stuff
|
||||
; R17: recv buffer. Whenever we receive a bit, we push it in there.
|
||||
; R18: recv step:
|
||||
; - 0: idle
|
||||
; - 1: receiving data
|
||||
; - 2: awaiting parity bit
|
||||
; - 3: awaiting stop bit
|
||||
; R19: Register used for parity computations and tmp value in some other places
|
||||
; R20: data being sent to the '164
|
||||
; Y: pointer to the memory location where the next scan code from ps/2 will be
|
||||
; written.
|
||||
; Z: pointer to the next scan code to push to the 595
|
||||
;
|
||||
; *** Constants ***
|
||||
.equ CLK = PINB2
|
||||
.equ DATA = PINB1
|
||||
.equ CP = PINB3
|
||||
; SR-Latch's Q pin
|
||||
.equ LQ = PINB0
|
||||
; SR-Latch's R pin
|
||||
.equ LR = PINB4
|
||||
|
||||
; init value for TCNT0 so that overflow occurs in 100us
|
||||
.equ TIMER_INITVAL = 0x100-100
|
||||
|
||||
; *** Code ***
|
||||
|
||||
rjmp main
|
||||
rjmp hdlINT0
|
||||
|
||||
; Read DATA and set GPIOR0/0 if high. Then, set flag T.
|
||||
; no SREG fiddling because no SREG-modifying instruction
|
||||
hdlINT0:
|
||||
sbic PINB, DATA ; DATA clear? skip next
|
||||
sbi GPIOR0, 0
|
||||
set
|
||||
reti
|
||||
|
||||
main:
|
||||
ldi r16, low(RAMEND)
|
||||
out SPL, r16
|
||||
ldi r16, high(RAMEND)
|
||||
out SPH, r16
|
||||
|
||||
; init variables
|
||||
clr r18
|
||||
out GPIOR0, r18
|
||||
|
||||
; Setup int0
|
||||
; INT0, falling edge
|
||||
ldi r16, (1<<ISC01)
|
||||
out MCUCR, r16
|
||||
; Enable INT0
|
||||
ldi r16, (1<<INT0)
|
||||
out GIMSK, r16
|
||||
|
||||
; Setup buffer
|
||||
clr YH
|
||||
ldi YL, low(SRAM_START)
|
||||
clr ZH
|
||||
ldi ZL, low(SRAM_START)
|
||||
|
||||
; Setup timer. We use the timer to clear up "processbit" registers after
|
||||
; 100us without a clock. This allows us to start the next frame in a
|
||||
; fresh state. at 1MHZ, no prescaling is necessary. Each TCNT0 tick is
|
||||
; already 1us long.
|
||||
ldi r16, (1<<CS00) ; no prescaler
|
||||
out TCCR0B, r16
|
||||
|
||||
; init DDRB
|
||||
sbi DDRB, CP
|
||||
cbi PORTB, LR
|
||||
sbi DDRB, LR
|
||||
|
||||
sei
|
||||
|
||||
loop:
|
||||
brts processbit ; flag T set? we have a bit to process
|
||||
cp YL, ZL ; if YL == ZL, buffer is empty
|
||||
brne sendTo164 ; YL != ZL? our buffer has data
|
||||
|
||||
; nothing to do. Before looping, let's check if our communication timer
|
||||
; overflowed.
|
||||
in r16, TIFR
|
||||
sbrc r16, TOV0
|
||||
rjmp processbitReset ; Timer0 overflow? reset processbit
|
||||
|
||||
; Nothing to do for real.
|
||||
rjmp loop
|
||||
|
||||
; Process the data bit received in INT0 handler.
|
||||
processbit:
|
||||
in r19, GPIOR0 ; backup GPIOR0 before we reset T
|
||||
andi r19, 0x1 ; only keep the first flag
|
||||
cbi GPIOR0, 0
|
||||
clt ; ready to receive another bit
|
||||
|
||||
; We've received a bit. reset timer
|
||||
rcall resetTimer
|
||||
|
||||
; Which step are we at?
|
||||
tst r18
|
||||
breq processbits0
|
||||
cpi r18, 1
|
||||
breq processbits1
|
||||
cpi r18, 2
|
||||
breq processbits2
|
||||
; step 3: stop bit
|
||||
clr r18 ; happens in all cases
|
||||
; DATA has to be set
|
||||
tst r19 ; Was DATA set?
|
||||
breq loop ; not set? error, don't push to buffer
|
||||
; push r17 to the buffer
|
||||
st Y+, r17
|
||||
rcall checkBoundsY
|
||||
rjmp loop
|
||||
|
||||
processbits0:
|
||||
; step 0 - start bit
|
||||
; DATA has to be cleared
|
||||
tst r19 ; Was DATA set?
|
||||
brne loop ; Set? error. no need to do anything. keep r18
|
||||
; as-is.
|
||||
; DATA is cleared. prepare r17 and r18 for step 1
|
||||
inc r18
|
||||
ldi r17, 0x80
|
||||
rjmp loop
|
||||
|
||||
processbits1:
|
||||
; step 1 - receive bit
|
||||
; We're about to rotate the carry flag into r17. Let's set it first
|
||||
; depending on whether DATA is set.
|
||||
clc
|
||||
sbrc r19, 0 ; skip if DATA cleared.
|
||||
sec
|
||||
; Carry flag is set
|
||||
ror r17
|
||||
; Good. now, are we finished rotating? If carry flag is set, it means
|
||||
; that we've rotated in 8 bits.
|
||||
brcc loop ; we haven't finished yet
|
||||
; We're finished, go to step 2
|
||||
inc r18
|
||||
rjmp loop
|
||||
processbits2:
|
||||
; step 2 - parity bit
|
||||
mov r1, r19
|
||||
mov r19, r17
|
||||
rcall checkParity ; --> r16
|
||||
cp r1, r16
|
||||
brne processbitError ; r1 != r16? wrong parity
|
||||
inc r18
|
||||
rjmp loop
|
||||
|
||||
processbitError:
|
||||
clr r18
|
||||
ldi r19, 0xfe
|
||||
rcall sendToPS2
|
||||
rjmp loop
|
||||
|
||||
processbitReset:
|
||||
clr r18
|
||||
rcall resetTimer
|
||||
rjmp loop
|
||||
|
||||
; Send the value of r20 to the '164
|
||||
sendTo164:
|
||||
sbis PINB, LQ ; LQ is set? we can send the next byte
|
||||
rjmp loop ; Even if we have something in the buffer, we
|
||||
; can't: the SMS hasn't read our previous
|
||||
; buffer yet.
|
||||
; We disable any interrupt handling during this routine. Whatever it
|
||||
; is, it has no meaning to us at this point in time and processing it
|
||||
; might mess things up.
|
||||
cli
|
||||
sbi DDRB, DATA
|
||||
|
||||
ld r20, Z+
|
||||
rcall checkBoundsZ
|
||||
ldi r16, 8
|
||||
|
||||
sendTo164Loop:
|
||||
cbi PORTB, DATA
|
||||
sbrc r20, 7 ; if leftmost bit isn't cleared, set DATA high
|
||||
sbi PORTB, DATA
|
||||
; toggle CP
|
||||
cbi PORTB, CP
|
||||
lsl r20
|
||||
sbi PORTB, CP
|
||||
dec r16
|
||||
brne sendTo164Loop ; not zero yet? loop
|
||||
|
||||
; release PS/2
|
||||
cbi DDRB, DATA
|
||||
sei
|
||||
|
||||
; Reset the latch to indicate that the next number is ready
|
||||
sbi PORTB, LR
|
||||
cbi PORTB, LR
|
||||
rjmp loop
|
||||
|
||||
resetTimer:
|
||||
ldi r16, TIMER_INITVAL
|
||||
out TCNT0, r16
|
||||
ldi r16, (1<<TOV0)
|
||||
out TIFR, r16
|
||||
ret
|
||||
|
||||
; Send the value of r19 to the PS/2 keyboard
|
||||
sendToPS2:
|
||||
cli
|
||||
|
||||
; First, indicate our request to send by holding both Clock low for
|
||||
; 100us, then pull Data low
|
||||
; lines low for 100us.
|
||||
cbi PORTB, CLK
|
||||
sbi DDRB, CLK
|
||||
rcall resetTimer
|
||||
|
||||
; Wait until the timer overflows
|
||||
in r16, TIFR
|
||||
sbrs r16, TOV0
|
||||
rjmp PC-2
|
||||
; Good, 100us passed.
|
||||
|
||||
; Pull Data low, that's our start bit.
|
||||
cbi PORTB, DATA
|
||||
sbi DDRB, DATA
|
||||
|
||||
; Now, let's release the clock. At the next raising edge, we'll be
|
||||
; expected to have set up our first bit (LSB). We set up when CLK is
|
||||
; low.
|
||||
cbi DDRB, CLK ; Should be starting high now.
|
||||
|
||||
; We will do the next loop 8 times
|
||||
ldi r16, 8
|
||||
; Let's remember initial r19 for parity
|
||||
mov r1, r19
|
||||
|
||||
sendToPS2Loop:
|
||||
; Wait for CLK to go low
|
||||
sbic PINB, CLK
|
||||
rjmp PC-1
|
||||
|
||||
; set up DATA
|
||||
cbi PORTB, DATA
|
||||
sbrc r19, 0 ; skip if LSB is clear
|
||||
sbi PORTB, DATA
|
||||
lsr r19
|
||||
|
||||
; Wait for CLK to go high
|
||||
sbis PINB, CLK
|
||||
rjmp PC-1
|
||||
|
||||
dec r16
|
||||
brne sendToPS2Loop ; not zero? loop
|
||||
|
||||
; Data was sent, CLK is high. Let's send parity
|
||||
mov r19, r1 ; recall saved value
|
||||
rcall checkParity ; --> r16
|
||||
|
||||
; Wait for CLK to go low
|
||||
sbic PINB, CLK
|
||||
rjmp PC-1
|
||||
|
||||
; set parity bit
|
||||
cbi PORTB, DATA
|
||||
sbrc r16, 0 ; parity bit in r16
|
||||
sbi PORTB, DATA
|
||||
|
||||
; Wait for CLK to go high
|
||||
sbis PINB, CLK
|
||||
rjmp PC-1
|
||||
|
||||
; Wait for CLK to go low
|
||||
sbic PINB, CLK
|
||||
rjmp PC-1
|
||||
|
||||
; We can now release the DATA line
|
||||
cbi DDRB, DATA
|
||||
|
||||
; Wait for DATA to go low. That's our ACK
|
||||
sbic PINB, DATA
|
||||
rjmp PC-1
|
||||
|
||||
; Wait for CLK to go low
|
||||
sbic PINB, CLK
|
||||
rjmp PC-1
|
||||
|
||||
; We're finished! Enable INT0, reset timer, everything back to normal!
|
||||
rcall resetTimer
|
||||
clt ; also, make sure T isn't mistakely set.
|
||||
sei
|
||||
ret
|
||||
|
||||
; Check that Y is within bounds, reset to SRAM_START if not.
|
||||
checkBoundsY:
|
||||
tst YL
|
||||
breq PC+2
|
||||
ret ; not zero, nothing to do
|
||||
; YL is zero. Reset Y
|
||||
clr YH
|
||||
ldi YL, low(SRAM_START)
|
||||
ret
|
||||
|
||||
; Check that Z is within bounds, reset to SRAM_START if not.
|
||||
checkBoundsZ:
|
||||
tst ZL
|
||||
breq PC+2
|
||||
ret ; not zero, nothing to do
|
||||
; ZL is zero. Reset Z
|
||||
clr ZH
|
||||
ldi ZL, low(SRAM_START)
|
||||
ret
|
||||
|
||||
; Counts the number of 1s in r19 and set r16 to 1 if there's an even number of
|
||||
; 1s, 0 if they're odd.
|
||||
checkParity:
|
||||
ldi r16, 1
|
||||
lsr r19
|
||||
brcc PC+2 ; Carry unset? skip next
|
||||
inc r16 ; Carry set? We had a 1
|
||||
tst r19 ; is r19 zero yet?
|
||||
brne checkParity+1 ; no? loop and skip first LDI
|
||||
andi r16, 0x1 ; Sets Z accordingly
|
||||
ret
|
||||
|
||||
Loading…
Reference in New Issue