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https://github.com/hsoft/collapseos.git
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432 lines
11 KiB
NASM
432 lines
11 KiB
NASM
.include "tn45def.inc"
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; Receives keystrokes from PS/2 keyboard and send them to the 595. As long as
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; that number is not collected, we buffer the scan code received from ps/2. As
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; soon as that number is collected we put the next number in the buffer. If the
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; buffer is empty, we do nothing (the 595 already had its SRCLR pin triggered
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; and shows 0).
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;
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; PS/2 is a bidirectional protocol, but in this program, we only care about
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; receiving keystrokes. We don't send anything to the keyboard.
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;
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; The PS/2 keyboard has two data wires: Clock and Data. It is the keyboard that
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; drives the clock with about 30-50 us between each clock.
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;
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; We wire the Clock to INT0 (PB2) and make it trigger an interrupt on the
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; falling edge (the edge, in the PS/2 protocol, when data is set).
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;
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; Data is sent by the keyboard in 11-bit frames. 1 start bit (0), 8 data bits,
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; one parity bit, one stop bit (1).
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;
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; Parity bit is set if number of bits in data bits is even. Unset otherwise.
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;
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; *** Receiving a data frame ***
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;
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; In idle mode, R18 is zero. When INT0 is triggered, it is increased and R17 is
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; loaded with 0x80. We do this because we're going to right shift our data in
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; (byte is sent LSB first). When the carry flag is set, we'll know we're
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; finished. When that happens, we increase R18 again. We're waiting for parity
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; bit. When we get it, we check parity and increase R18 again. We're waiting
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; for stop bit. After we receive stop bit, we reset R18 to 0.
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;
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; On error, we ignore and reset our counters.
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; *** Buffering scan codes ***
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;
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; The buffer starts at SRAM and stops at 0x100. It leaves space for the stack
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; and makes overflow check easy. Also, we don't need a very big buffer. In this
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; address space, Z chasing Y. When Y == Z, the buffer is empty. When 0x100 is
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; reached, we go back to SRAM_START.
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;
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; Whenever a new scan code is received, we place it in Y and increase it.
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; Whenever we send a scan code to the 595 (which can't be done when Z == Y
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; because Z points to an invalid value), we send the value of Z and increase.
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; *** Sending to the 595 ***
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;
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; Whenever a scan code is read from the 595, CE goes low and triggers a PCINT
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; on PB4. When we get it, we clear the GPIOR0/1 flag to indicate that we're
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; ready to send a new scan code to the 595.
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;
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; Because that CE flip/flop is real fast (375ns), it requires us to run at 8MHz.
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;
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; During the PCINT, we also trigger RCLK once because CE is also wired to SRCLR
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; and we want the z80 to be able to know that the device has nothing to give
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; (has a value of zero) rather than having to second guess (is this value, which
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; is the same as the one that was read before, a new value or not?). With that
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; "quick zero-in" scheme, there's no ambiguity: no scan code can be ready twice
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; because it's replaced by a 0 as soon as it's read, until it can be filled with
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; the next char in the buffer.
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; *** Register Usage ***
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;
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; GPIOR0 flags:
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; 0 - when set, indicates that the DATA pin was high when we received a
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; bit through INT0. When we receive a bit, we set flag T to indicate
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; it.
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; 1 - When set, indicate that the 595 holds a value that hasn't been read
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; by the z80 yet.
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;
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; R16: tmp stuff
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; R17: recv buffer. Whenever we receive a bit, we push it in there.
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; R18: recv step:
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; - 0: idle
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; - 1: receiving data
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; - 2: awaiting parity bit
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; - 3: awaiting stop bit
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; R19: Register used for parity computations and tmp value in some other places
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; R20: data being sent to the 595
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; Y: pointer to the memory location where the next scan code from ps/2 will be
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; written.
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; Z: pointer to the next scan code to push to the 595
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;
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; *** Constants ***
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;
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.equ CLK = PINB2
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.equ DATA = PINB1
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.equ SRCLK = PINB3
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.equ CE = PINB4
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.equ RCLK = PINB0
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; init value for TCNT0 so that overflow occurs in 100us
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.equ TIMER_INITVAL = 0x100-100
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rjmp main
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rjmp hdlINT0
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rjmp hdlPCINT
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; Read DATA and set GPIOR0/0 if high. Then, set flag T.
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; no SREG fiddling because no SREG-modifying instruction
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hdlINT0:
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sbic PINB, DATA ; DATA clear? skip next
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sbi GPIOR0, 0
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set
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reti
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; Only PB4 is hooked to PCINT and we don't bother checking the value of the PB4
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; pin: things go too fast for this.
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; no SREG fiddling because no SREG-modifying instruction
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hdlPCINT:
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; SRCLR has been triggered. Let's trigger RCLK too.
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sbi PORTB, RCLK
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cbi PORTB, RCLK
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cbi GPIOR0, 1 ; 595 is now free
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reti
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main:
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ldi r16, low(RAMEND)
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out SPL, r16
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ldi r16, high(RAMEND)
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out SPH, r16
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; Set clock prescaler to 1 (8MHz)
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ldi r16, (1<<CLKPCE)
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out CLKPR, r16
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clr r16
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out CLKPR, r16
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; init variables
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clr r18
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out GPIOR0, r18
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; Setup int0/PCINT
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; INT0, falling edge
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ldi r16, (1<<ISC01)
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out MCUCR, r16
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; Enable both INT0 and PCINT
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ldi r16, (1<<INT0)|(1<<PCIE)
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out GIMSK, r16
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; For PCINT, enable only PB4
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ldi r16, (1<<PCINT4)
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out PCMSK, r16
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; Setup buffer
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clr YH
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ldi YL, low(SRAM_START)
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clr ZH
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ldi ZL, low(SRAM_START)
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; Setup timer. We use the timer to clear up "processbit" registers after
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; 100us without a clock. This allows us to start the next frame in a
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; fresh state. at 8MHZ, setting the counter's prescaler to 8 gives us
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; a nice 1us for each TCNT0.
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ldi r16, (1<<CS01) ; clk/8 prescaler
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out TCCR0B, r16
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; init DDRB
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sbi DDRB, SRCLK
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cbi PORTB, RCLK ; RCLK is generally kept low
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sbi DDRB, RCLK
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sei
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loop:
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brts processbit ; flag T set? we have a bit to process
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cp YL, ZL ; if YL == ZL, buffer is empty
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brne sendTo595 ; YL != ZL? our buffer has data
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; nothing to do. Before looping, let's check if our communication timer
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; overflowed.
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in r16, TIFR
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sbrc r16, TOV0
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rjmp processbitReset ; Timer0 overflow? reset processbit
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; Nothing to do for real.
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rjmp loop
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; Process the data bit received in INT0 handler.
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processbit:
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in r19, GPIOR0 ; backup GPIOR0 before we reset T
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andi r19, 0x1 ; only keep the first flag
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cbi GPIOR0, 0
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clt ; ready to receive another bit
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; We've received a bit. reset timer
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rcall resetTimer
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; Which step are we at?
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tst r18
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breq processbits0
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cpi r18, 1
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breq processbits1
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cpi r18, 2
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breq processbits2
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; step 3: stop bit
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clr r18 ; happens in all cases
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; DATA has to be set
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tst r19 ; Was DATA set?
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breq loop ; not set? error, don't push to buffer
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; push r17 to the buffer
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st Y+, r17
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rcall checkBoundsY
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rjmp loop
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processbits0:
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; step 0 - start bit
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; DATA has to be cleared
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tst r19 ; Was DATA set?
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brne loop ; Set? error. no need to do anything. keep r18
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; as-is.
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; DATA is cleared. prepare r17 and r18 for step 1
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inc r18
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ldi r17, 0x80
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rjmp loop
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processbits1:
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; step 1 - receive bit
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; We're about to rotate the carry flag into r17. Let's set it first
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; depending on whether DATA is set.
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clc
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sbrc r19, 0 ; skip if DATA cleared.
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sec
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; Carry flag is set
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ror r17
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; Good. now, are we finished rotating? If carry flag is set, it means
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; that we've rotated in 8 bits.
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brcc loop ; we haven't finished yet
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; We're finished, go to step 2
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inc r18
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rjmp loop
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processbits2:
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; step 2 - parity bit
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mov r1, r19
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mov r19, r17
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rcall checkParity ; --> r16
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cp r1, r16
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brne processbitError ; r1 != r16? wrong parity
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inc r18
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rjmp loop
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processbitError:
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clr r18
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ldi r19, 0xfe
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rcall sendToPS2
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rjmp loop
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processbitReset:
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clr r18
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rcall resetTimer
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rjmp loop
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; send next scan code in buffer to 595, MSB.
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sendTo595:
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sbic GPIOR0, 1
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rjmp loop ; flag 1 set? 595 is "busy". Don't send.
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; We disable any interrupt handling during this routine. Whatever it
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; is, it has no meaning to us at this point in time and processing it
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; might mess things up.
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cli
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sbi DDRB, DATA
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ld r20, Z+
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rcall checkBoundsZ
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ldi r16, 8
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sendTo595Loop:
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cbi PORTB, DATA
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sbrc r20, 7 ; if leftmost bit isn't cleared, set DATA high
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sbi PORTB, DATA
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; toggle SRCLK
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cbi PORTB, SRCLK
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lsl r20
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sbi PORTB, SRCLK
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dec r16
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brne sendTo595Loop ; not zero yet? loop
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; We're finished sending our data to the 595 and we're ready to go back
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; to business as usual. However, timing is important here. The z80 is
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; very fast and constantly hammers our 595 with polls. While this
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; routine was running, it was getting zeroes, which is fine, but as soon
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; as we trigger RCLK, the z80 is going to fetch that value. What we want
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; to do is to enable back the interrupts as soon as RCLK is triggered
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; so that the z80 doesn't have enough time to poll twice. If it did, we
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; would return a double character. This is why RCLK triggering is the
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; last operation.
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; release PS/2
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cbi DDRB, DATA
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; Set GPIOR0/1 to "595 is busy"
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sbi GPIOR0, 1
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; toggle RCLK
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sbi PORTB, RCLK
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cbi PORTB, RCLK
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sei
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rjmp loop
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resetTimer:
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ldi r16, TIMER_INITVAL
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out TCNT0, r16
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ldi r16, (1<<TOV0)
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out TIFR, r16
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ret
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; Send the value of r19 to the PS/2 keyboard
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sendToPS2:
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; We don't use the general INT0 mechanism here. However, we still want
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; to listen to PCINT, so we don't disable interrupts entirely, just
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; INT0.
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ldi r16, (1<<PCIE)
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out GIMSK, r16
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; First, indicate our request to send by holding both Clock low for
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; 100us, then pull Data low
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; lines low for 100us.
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cbi PORTB, CLK
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sbi DDRB, CLK
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rcall resetTimer
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; Wait until the timer overflows
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in r16, TIFR
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sbrs r16, TOV0
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rjmp PC-2
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; Good, 100us passed.
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; Pull Data low, that's our start bit.
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cbi PORTB, DATA
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sbi DDRB, DATA
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; Now, let's release the clock. At the next raising edge, we'll be
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; expected to have set up our first bit (LSB). We set up when CLK is
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; low.
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cbi DDRB, CLK ; Should be starting high now.
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; We will do the next loop 8 times
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ldi r16, 8
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; Let's remember initial r19 for parity
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mov r1, r19
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sendToPS2Loop:
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; set up DATA
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cbi PORTB, DATA
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sbrc r19, 0 ; skip if LSB is clear
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sbi PORTB, DATA
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lsr r19
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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dec r16
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brne sendToPS2Loop ; not zero? loop
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; Data was sent, CLK is high. Let's send parity
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mov r19, r1 ; recall saved value
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rcall checkParity ; --> r16
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; set parity bit
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cbi PORTB, DATA
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sbrc r16, 0 ; parity bit in r16
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sbi PORTB, DATA
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; We can now release the DATA line
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cbi DDRB, DATA
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; Wait for DATA to go low. That's our ACK
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sbic PINB, DATA
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rjmp PC-1
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; We're finished! Enable INT0, reset timer, everything back to normal!
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rcall resetTimer
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clt ; also, make sure T isn't mistakely set.
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ldi r16, (1<<INT0)|(1<<PCIE)
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out GIMSK, r16
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ret
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; Check that Y is within bounds, reset to SRAM_START if not.
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checkBoundsY:
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tst YL
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breq PC+2
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ret ; not zero, nothing to do
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; YL is zero. Reset Y
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clr YH
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ldi YL, low(SRAM_START)
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ret
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; Check that Z is within bounds, reset to SRAM_START if not.
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checkBoundsZ:
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tst ZL
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breq PC+2
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ret ; not zero, nothing to do
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; ZL is zero. Reset Z
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clr ZH
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ldi ZL, low(SRAM_START)
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ret
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; Counts the number of 1s in r19 and set r16 to 1 if there's an even number of
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; 1s, 0 if they're odd.
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checkParity:
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ldi r16, 1
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lsr r19
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brcc PC+2 ; Carry unset? skip next
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inc r16 ; Carry set? We had a 1
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tst r19 ; is r19 zero yet?
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brne checkParity+1 ; no? loop and skip first LDI
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andi r16, 0x1 ; Sets Z accordingly
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ret
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