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aa8df95f7d
...
ab578159b7
@ -62,12 +62,8 @@ instrNames:
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.equ I_RCALL 42
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.equ I_RCALL 42
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.db "RCALL", 0
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.db "RCALL", 0
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.db "RJMP", 0
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.db "RJMP", 0
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.equ I_IN 44
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.db "IN", 0
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.equ I_OUT 45
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.db "OUT", 0
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; no arg (from here, instrUpMasks2)
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; no arg (from here, instrUpMasks2)
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.equ I_BREAK 46
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.equ I_BREAK 44
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.db "BREAK", 0
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.db "BREAK", 0
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.db "CLC", 0
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.db "CLC", 0
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.db "CLH", 0
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.db "CLH", 0
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@ -95,7 +91,7 @@ instrNames:
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.db "SLEEP", 0
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.db "SLEEP", 0
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.db "WDR", 0
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.db "WDR", 0
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; Rd(5)
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; Rd(5)
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.equ I_ASR 72
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.equ I_ASR 70
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.db "ASR", 0
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.db "ASR", 0
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.db "COM", 0
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.db "COM", 0
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.db "DEC", 0
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.db "DEC", 0
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@ -147,9 +143,6 @@ instrUpMasks1:
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; k(12): XXXXkkkk kkkkkkkk
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; k(12): XXXXkkkk kkkkkkkk
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.db 0b11010000 ; RCALL
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.db 0b11010000 ; RCALL
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.db 0b11000000 ; RJMP
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.db 0b11000000 ; RJMP
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; IN and OUT
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.db 0b10110000 ; IN
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.db 0b10111000 ; OUT
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; 16-bit constant masks associated with each instruction. In the same order as
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; 16-bit constant masks associated with each instruction. In the same order as
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; in instrNames
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; in instrNames
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@ -246,11 +239,8 @@ parseInstruction:
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jr c, .spitRdK8
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jr c, .spitRdK8
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cp I_RCALL
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cp I_RCALL
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jr c, .spitRdBit
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jr c, .spitRdBit
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cp I_IN
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cp I_BREAK
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jr c, .spitK12
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jr c, .spitK12
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jp z, .spitIN
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cp I_OUT
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jp z, .spitOUT
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cp I_ASR
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cp I_ASR
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jr c, .spitNoArg
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jr c, .spitNoArg
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; spitRd5
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; spitRd5
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@ -283,7 +273,7 @@ parseInstruction:
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ld b, a
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ld b, a
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call .getUp1
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call .getUp1
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; now that's our MSB
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; now that's our MSB
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jp .spitMSB
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jr .spitMSB
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.spitRdK8:
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.spitRdK8:
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ld ix, argSpecs+6 ; 'r', 8
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ld ix, argSpecs+6 ; 'r', 8
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@ -303,7 +293,7 @@ parseInstruction:
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rra \ rra \ rra \ rra
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rra \ rra \ rra \ rra
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ld b, a
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ld b, a
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call .getUp1
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call .getUp1
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jp .spitMSB
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jr .spitMSB
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|
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.spitRdBit:
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.spitRdBit:
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ld ix, argSpecs+8 ; 'R', 'b'
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ld ix, argSpecs+8 ; 'R', 'b'
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@ -347,36 +337,6 @@ parseInstruction:
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or b
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or b
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jp ioPutB
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jp ioPutB
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.spitOUT:
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ld ix, argSpecs+12 ; 'A', 'R'
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call _parseArgs
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ret nz
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ld a, h
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ld h, l
|
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ld l, a
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jr .spitINOUT
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.spitIN:
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ld ix, argSpecs+14 ; 'R', 'A'
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call _parseArgs
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ret nz
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.spitINOUT:
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; Rd in H, A in L
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ld a, h
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call .placeRd
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ld a, l
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and 0xf
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or c
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; LSB ready
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call ioPutB
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; The two high bits of A go in bits 3:1 of MSB
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ld a, l
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rra \ rra \ rra
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and 0b110
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or b
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ld b, a
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; MSB is almost ready
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call .getUp1
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jr .spitMSB
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.spit:
|
.spit:
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; LSB is spit *before* MSB
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; LSB is spit *before* MSB
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inc hl
|
inc hl
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@ -489,8 +449,6 @@ argSpecs:
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.db 'r', 8 ; Rd(4) + K(8)
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.db 'r', 8 ; Rd(4) + K(8)
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.db 'R', 'b' ; Rd(5) + bit
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.db 'R', 'b' ; Rd(5) + bit
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.db 'b', 7 ; bit + k(7)
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.db 'b', 7 ; bit + k(7)
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.db 'A', 'R' ; A(6) + Rr(5)
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.db 'R', 'A' ; Rd(5) + A(6)
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|
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; Parse arguments in (HL) according to specs in IX
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; Parse arguments in (HL) according to specs in IX
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; Puts the results in HL (which is not needed anymore after the parsing).
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; Puts the results in HL (which is not needed anymore after the parsing).
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@ -535,44 +493,25 @@ _parseArgs:
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jr z, _readR4
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jr z, _readR4
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cp 'b'
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cp 'b'
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jr z, _readBit
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jr z, _readBit
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cp 'A'
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jr z, _readA6
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cp 7
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cp 7
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jr z, _readk7
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jr z, _readk7
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cp 8
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cp 8
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jr z, _readK8
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jr z, _readK8
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ret ; something's wrong
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ret ; something's wrong
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|
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; Read expr and return success only if result in under number given in A
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_readBit:
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; Z for success
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_readExpr:
|
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push ix
|
push ix
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push bc
|
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ld b, a
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call parseExpr
|
call parseExpr
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jr nz, .end
|
ld a, 7
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ld a, b
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call _IX2A
|
call _IX2A
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jr nz, .end
|
jr nz, .end
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or c
|
or c
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ld c, a
|
ld c, a
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cp a ; ensure Z
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cp a ; ensure Z
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.end:
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.end:
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pop bc
|
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pop ix
|
pop ix
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ret
|
ret
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|
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||||||
_readBit:
|
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ld a, 7
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jr _readExpr
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|
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_readA6:
|
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ld a, 0x3f
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|
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_readK8:
|
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ld a, 0xff
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jr _readExpr
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|
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_readk7:
|
_readk7:
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push hl
|
push hl
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push de
|
push de
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@ -610,6 +549,16 @@ _readk7:
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call unsetZ
|
call unsetZ
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||||||
jr .end
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jr .end
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||||||
|
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|
_readK8:
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|
push ix
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|
call parseExpr
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jr nz, .end
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ld a, 0xff
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call _IX2A
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.end:
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pop ix
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ret
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|
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_readR4:
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_readR4:
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call _readR5
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call _readR5
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ret nz
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ret nz
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@ -1,16 +0,0 @@
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# AVR include files
|
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||||||
|
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||||||
This folder contains header files that can be included in AVR assembly code.
|
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||||||
|
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||||||
These definitions are organized in a manner that is very similar to other
|
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||||||
modern AVR assemblers, but most bits definitions (`PINB4`, `WGM01`, etc.) are
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||||||
absent. This is because there's a lot of them, each symbol takes memory during
|
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||||||
assembly and machines doing the assembling might be tight in memory. AVR code
|
|
||||||
post collapse will have to take the habit of using numerical masks accompanied
|
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||||||
by comments describing associated symbols.
|
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||||||
|
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||||||
To avoid repeats, those includes are organized in 3 levels. First, there's the
|
|
||||||
`avr.h` file containing definitions common to all AVR models. Then, there's the
|
|
||||||
"family" file containing definitions common to a "family" (for example, the
|
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||||||
ATtiny 25/45/85). Those definitions are the beefiests. Then, there's the exact
|
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||||||
model file, which will typically contain RAM and Flash boundaries.
|
|
17
avr/avr.h
17
avr/avr.h
@ -1,17 +0,0 @@
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|||||||
; *** CPU registers aliases ***
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||||||
|
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.equ XH 27
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.equ XL 26
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||||||
.equ YH 29
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.equ YL 28
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.equ ZH 31
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||||||
.equ ZL 30
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||||||
|
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.equ SREG_C 0 ; Carry Flag
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||||||
.equ SREG_Z 1 ; Zero Flag
|
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.equ SREG_N 2 ; Negative Flag
|
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||||||
.equ SREG_V 3 ; Two's Complement Overflow Flag
|
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.equ SREG_S 4 ; Sign Bit
|
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||||||
.equ SREG_H 5 ; Half Carry Flag
|
|
||||||
.equ SREG_T 6 ; Bit Copy Storage
|
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||||||
.equ SREG_I 7 ; Global Interrupt Enable
|
|
10
avr/tn25.h
10
avr/tn25.h
@ -1,10 +0,0 @@
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|||||||
.equ FLASHEND 0x03ff ; Note: Word address
|
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||||||
.equ IOEND 0x003f
|
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||||||
.equ SRAM_START 0x0060
|
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||||||
.equ SRAM_SIZE 128
|
|
||||||
.equ RAMEND 0x00df
|
|
||||||
.equ XRAMEND 0x0000
|
|
||||||
.equ E2END 0x007f
|
|
||||||
.equ EEPROMEND 0x007f
|
|
||||||
.equ EEADRBITS 7
|
|
||||||
|
|
@ -1,74 +0,0 @@
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|||||||
; *** Registers ***
|
|
||||||
|
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||||||
.equ SREG 0x3f
|
|
||||||
.equ SPH 0x3e
|
|
||||||
.equ SPL 0x3d
|
|
||||||
.equ GIMSK 0x3b
|
|
||||||
.equ GIFR 0x3a
|
|
||||||
.equ TIMSK 0x39
|
|
||||||
.equ TIFR 0x38
|
|
||||||
.equ SPMCSR 0x37
|
|
||||||
.equ MCUCR 0x35
|
|
||||||
.equ MCUSR 0x34
|
|
||||||
.equ TCCR0B 0x33
|
|
||||||
.equ TCNT0 0x32
|
|
||||||
.equ OSCCAL 0x31
|
|
||||||
.equ TCCR1 0x30
|
|
||||||
.equ TCNT1 0x2f
|
|
||||||
.equ OCR1A 0x2e
|
|
||||||
.equ OCR1C 0x2d
|
|
||||||
.equ GTCCR 0x2c
|
|
||||||
.equ OCR1B 0x2b
|
|
||||||
.equ TCCR0A 0x2a
|
|
||||||
.equ OCR0A 0x29
|
|
||||||
.equ OCR0B 0x28
|
|
||||||
.equ PLLCSR 0x27
|
|
||||||
.equ CLKPR 0x26
|
|
||||||
.equ DT1A 0x25
|
|
||||||
.equ DT1B 0x24
|
|
||||||
.equ DTPS 0x23
|
|
||||||
.equ DWDR 0x22
|
|
||||||
.equ WDTCR 0x21
|
|
||||||
.equ PRR 0x20
|
|
||||||
.equ EEARH 0x1f
|
|
||||||
.equ EEARL 0x1e
|
|
||||||
.equ EEDR 0x1d
|
|
||||||
.equ EECR 0x1c
|
|
||||||
.equ PORTB 0x18
|
|
||||||
.equ DDRB 0x17
|
|
||||||
.equ PINB 0x16
|
|
||||||
.equ PCMSK 0x15
|
|
||||||
.equ DIDR0 0x14
|
|
||||||
.equ GPIOR2 0x13
|
|
||||||
.equ GPIOR1 0x12
|
|
||||||
.equ GPIOR0 0x11
|
|
||||||
.equ USIBR 0x10
|
|
||||||
.equ USIDR 0x0f
|
|
||||||
.equ USISR 0x0e
|
|
||||||
.equ USICR 0x0d
|
|
||||||
.equ ACSR 0x08
|
|
||||||
.equ ADMUX 0x07
|
|
||||||
.equ ADCSRA 0x06
|
|
||||||
.equ ADCH 0x05
|
|
||||||
.equ ADCL 0x04
|
|
||||||
.equ ADCSRB 0x03
|
|
||||||
|
|
||||||
|
|
||||||
; *** Interrupt vectors ***
|
|
||||||
|
|
||||||
.equ INT0addr 0x0001 ; External Interrupt 0
|
|
||||||
.equ PCI0addr 0x0002 ; Pin change Interrupt Request 0
|
|
||||||
.equ OC1Aaddr 0x0003 ; Timer/Counter1 Compare Match 1A
|
|
||||||
.equ OVF1addr 0x0004 ; Timer/Counter1 Overflow
|
|
||||||
.equ OVF0addr 0x0005 ; Timer/Counter0 Overflow
|
|
||||||
.equ ERDYaddr 0x0006 ; EEPROM Ready
|
|
||||||
.equ ACIaddr 0x0007 ; Analog comparator
|
|
||||||
.equ ADCCaddr 0x0008 ; ADC Conversion ready
|
|
||||||
.equ OC1Baddr 0x0009 ; Timer/Counter1 Compare Match B
|
|
||||||
.equ OC0Aaddr 0x000a ; Timer/Counter0 Compare Match A
|
|
||||||
.equ OC0Baddr 0x000b ; Timer/Counter0 Compare Match B
|
|
||||||
.equ WDTaddr 0x000c ; Watchdog Time-out
|
|
||||||
.equ USI_STARTaddr 0x000d ; USI START
|
|
||||||
.equ USI_OVFaddr 0x000e ; USI Overflow
|
|
||||||
|
|
||||||
.equ INT_VECTORS_SIZE 15 ; size in words
|
|
@ -1,9 +0,0 @@
|
|||||||
.equ FLASHEND 0x07ff ; Note: Word address
|
|
||||||
.equ IOEND 0x003f
|
|
||||||
.equ SRAM_START 0x0060
|
|
||||||
.equ SRAM_SIZE 256
|
|
||||||
.equ RAMEND 0x015f
|
|
||||||
.equ XRAMEND 0x0000
|
|
||||||
.equ E2END 0x00ff
|
|
||||||
.equ EEPROMEND 0x00ff
|
|
||||||
.equ EEADRBITS 8
|
|
@ -1,9 +0,0 @@
|
|||||||
.equ FLASHEND 0x0fff ; Note: Word address
|
|
||||||
.equ IOEND 0x003f
|
|
||||||
.equ SRAM_START 0x0060
|
|
||||||
.equ SRAM_SIZE 512
|
|
||||||
.equ RAMEND 0x025f
|
|
||||||
.equ XRAMEND 0x0000
|
|
||||||
.equ E2END 0x01ff
|
|
||||||
.equ EEPROMEND 0x01ff
|
|
||||||
.equ EEADRBITS 9
|
|
@ -1,43 +0,0 @@
|
|||||||
; TODO: implement instructions that are commented out
|
|
||||||
; REGISTER USAGE
|
|
||||||
;
|
|
||||||
; R1: overflow counter
|
|
||||||
; R16: tmp stuff
|
|
||||||
|
|
||||||
.inc "avr.h"
|
|
||||||
.inc "tn254585.h"
|
|
||||||
.inc "tn45.h"
|
|
||||||
|
|
||||||
main:
|
|
||||||
ldi r16, RAMEND&0xff
|
|
||||||
out SPL, r16
|
|
||||||
ldi r16, RAMEND}8
|
|
||||||
out SPH, r16
|
|
||||||
|
|
||||||
;sbi DDRB, 0
|
|
||||||
;cbi PORTB, 0
|
|
||||||
|
|
||||||
; To have a blinking delay that's visible, we have to prescale a lot.
|
|
||||||
; The maximum prescaler is 1024, which makes our TCNT0 increase
|
|
||||||
; 976 times per second, which means that it overflows 4 times per
|
|
||||||
; second.
|
|
||||||
in r16, TCCR0B
|
|
||||||
ori r16, 0x05 ; CS00 + CS02 = 1024 prescaler
|
|
||||||
out TCCR0B, r16
|
|
||||||
|
|
||||||
;clr r1
|
|
||||||
|
|
||||||
loop:
|
|
||||||
in r16, TIFR ; TIFR0
|
|
||||||
sbrc r16, 1 ; is TOV0 flag clear?
|
|
||||||
rcall toggle
|
|
||||||
rjmp loop
|
|
||||||
|
|
||||||
toggle:
|
|
||||||
ldi r16, 0b00000010 ; TOV0
|
|
||||||
out TIFR, R16
|
|
||||||
inc r1
|
|
||||||
;cbi PORTB, 0
|
|
||||||
sbrs r1, 1 ; if LED is on
|
|
||||||
;sbi PORTB, 0
|
|
||||||
ret
|
|
@ -1 +0,0 @@
|
|||||||
å
¿à¿·`¿·ýÐüÏà¿”þ•
|
|
@ -1,12 +1,11 @@
|
|||||||
#!/bin/sh -e
|
#!/bin/sh -e
|
||||||
|
|
||||||
ZASM=../../zasm.sh
|
AVRA=../../emul/zasm/avra
|
||||||
AVRINC=../../../avr
|
|
||||||
|
|
||||||
cmpas() {
|
cmpas() {
|
||||||
FN=$1
|
FN=$1
|
||||||
EXPECTED=$(xxd ${FN%.*}.expected)
|
EXPECTED=$(xxd ${FN%.*}.expected)
|
||||||
ACTUAL=$(cat ${FN} | "${ZASM}" -a "${AVRINC}" | xxd)
|
ACTUAL=$(cat ${FN} | $AVRA | xxd)
|
||||||
if [ "$ACTUAL" = "$EXPECTED" ]; then
|
if [ "$ACTUAL" = "$EXPECTED" ]; then
|
||||||
echo ok
|
echo ok
|
||||||
else
|
else
|
||||||
|
@ -12,5 +12,3 @@ sbrs r1, 3
|
|||||||
rjmp foo
|
rjmp foo
|
||||||
rcall baz
|
rcall baz
|
||||||
baz:
|
baz:
|
||||||
out 0x2e, r12
|
|
||||||
in r0, 0x9
|
|
||||||
|
Binary file not shown.
@ -6,22 +6,15 @@
|
|||||||
# binary. For example, "zasm.sh -o 4f < foo.asm" assembles foo.asm as if it
|
# binary. For example, "zasm.sh -o 4f < foo.asm" assembles foo.asm as if it
|
||||||
# started with the line ".org 0x4f00".
|
# started with the line ".org 0x4f00".
|
||||||
|
|
||||||
# The -a flag makes us switch to the AVR assembler
|
|
||||||
|
|
||||||
# readlink -f doesn't work with macOS's implementation
|
# readlink -f doesn't work with macOS's implementation
|
||||||
# so, if we can't get readlink -f to work, try python with a realpath implementation
|
# so, if we can't get readlink -f to work, try python with a realpath implementation
|
||||||
ABS_PATH=$(readlink -f "$0" || python -c "import os; print(os.path.realpath('$0'))")
|
ABS_PATH=$(readlink -f "$0" || python -c "import os; print(os.path.realpath('$0'))")
|
||||||
DIR=$(dirname "${ABS_PATH}")
|
|
||||||
ZASMBIN="${DIR}/emul/zasm/zasm"
|
|
||||||
|
|
||||||
usage() { echo "Usage: $0 [-a] [-o <hexorg>] <paths-to-include>..." 1>&2; exit 1; }
|
usage() { echo "Usage: $0 [-o <hexorg>] <paths-to-include>..." 1>&2; exit 1; }
|
||||||
|
|
||||||
org='00'
|
org='00'
|
||||||
while getopts ":ao:" opt; do
|
while getopts ":o:" opt; do
|
||||||
case "${opt}" in
|
case "${opt}" in
|
||||||
a)
|
|
||||||
ZASMBIN="${DIR}/emul/zasm/avra"
|
|
||||||
;;
|
|
||||||
o)
|
o)
|
||||||
org=${OPTARG}
|
org=${OPTARG}
|
||||||
;;
|
;;
|
||||||
@ -33,6 +26,8 @@ done
|
|||||||
shift $((OPTIND-1))
|
shift $((OPTIND-1))
|
||||||
|
|
||||||
# wrapper around ./emul/zasm/zasm that prepares includes CFS prior to call
|
# wrapper around ./emul/zasm/zasm that prepares includes CFS prior to call
|
||||||
|
DIR=$(dirname "${ABS_PATH}")
|
||||||
|
ZASMBIN="${DIR}/emul/zasm/zasm"
|
||||||
CFSPACK="${DIR}/cfspack/cfspack"
|
CFSPACK="${DIR}/cfspack/cfspack"
|
||||||
INCCFS=$(mktemp)
|
INCCFS=$(mktemp)
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user