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sms/kbd: continue advancing on ps2ctl rewrite

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Still binary matching. Next step is branching support.
This commit is contained in:
Virgil Dupras 2020-05-17 21:10:02 -04:00
parent 177e70580f
commit 63dec372ce
4 changed files with 55 additions and 0 deletions
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1
blk/662
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@ -2,6 +2,7 @@
: _r8c DUP 7 > IF _oor THEN ; : _r8c DUP 7 > IF _oor THEN ;
: _r32c DUP 31 > IF _oor THEN ; : _r32c DUP 31 > IF _oor THEN ;
: _r16+c _r32c DUP 16 < IF _oor THEN ; : _r16+c _r32c DUP 16 < IF _oor THEN ;
: _r64c DUP 63 > IF _oor THEN ;
: _r256c DUP 255 > IF _oor THEN ; : _r256c DUP 255 > IF _oor THEN ;
: _Rdp ( op rd -- op', place Rd ) 4 LSHIFT OR ; : _Rdp ( op rd -- op', place Rd ) 4 LSHIFT OR ;

6
blk/664
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@ -7,3 +7,9 @@
0x14 OPRdRr CP, 0x04 OPRdRr CPC, 0x10 OPRdRr CPSE, 0x14 OPRdRr CP, 0x04 OPRdRr CPC, 0x10 OPRdRr CPSE,
0x24 OPRdRr EOR, 0x2c OPRdRr MOV, 0x9c OPRdRr MUL, 0x24 OPRdRr EOR, 0x2c OPRdRr MOV, 0x9c OPRdRr MUL,
0x28 OPRdRr OR, 0x08 OPRdRr SBC, 0x18 OPRdRr SUB, 0x28 OPRdRr OR, 0x08 OPRdRr SBC, 0x18 OPRdRr SUB,
( 0000 0AAd dddd AAAA )
: OPRdA CREATE C, DOES> C@ ( rd A op )
OVER _r64c 0x30 AND 3 RSHIFT OR ( rd A op' )
8 LSHIFT OR 0xff0f AND ( rd op' ) SWAP _r32c _Rdp A,, ;
0xb0 OPRdA IN, 0xb8 OPRdA _ : OUT, SWAP _ ;

3
blk/667
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@ -8,3 +8,6 @@
ROT _r32c _Rdp SWAP _r8c OR A,, ; ROT _r32c _Rdp SWAP _r8c OR A,, ;
0b1111100000000000 OPRdb BLD, 0b1111101000000000 OPRdb BST, 0b1111100000000000 OPRdb BLD, 0b1111101000000000 OPRdb BST,
0b1111110000000000 OPRdb SBRC, 0b1111111000000000 OPRdb SBRS, 0b1111110000000000 OPRdb SBRC, 0b1111111000000000 OPRdb SBRS,
( special cases )
: CLR, DUP EOR, ; : TST, DUP AND, ;

45
recipes/sms/kbd/ps2ctl.fs
View File

@ -32,10 +32,23 @@ Y: pointer to the memory location where the next scan code from
ps/2 will be written. ps/2 will be written.
Z: pointer to the next scan code to push to the 595 ) Z: pointer to the next scan code to push to the 595 )
0x0060 CONSTANT SRAM_START
0x015f CONSTANT RAMEND 0x015f CONSTANT RAMEND
0x3d CONSTANT SPL
0x3e CONSTANT SPH
0x11 CONSTANT GPIOR0 0x11 CONSTANT GPIOR0
0x35 CONSTANT MCUCR
0x33 CONSTANT TCCR0B
0x3b CONSTANT GIMSK
0x16 CONSTANT PINB 0x16 CONSTANT PINB
0x17 CONSTANT DDRB
0x18 CONSTANT PORTB
2 CONSTANT CLK
1 CONSTANT DATA 1 CONSTANT DATA
3 CONSTANT CP
0 CONSTANT LQ
4 CONSTANT LR
0x100-100 CONSTANT TIMER_INITVAL
H@ ORG ! H@ ORG !
L1 FLBL, ( main ) L1 FLBL, ( main )
@ -51,3 +64,35 @@ RETI,
RJMPOP L1 FLBL! ( main ) RJMPOP L1 FLBL! ( main )
16 RAMEND 0xff AND LDI, 16 RAMEND 0xff AND LDI,
SPL 16 OUT,
16 RAMEND 8 RSHIFT LDI,
SPH 16 OUT,
( init variables )
18 CLR,
GPIOR0 18 OUT,
( Setup int0
INT0, falling edge )
16 0x02 ( ISC01 ) LDI,
MCUCR 16 OUT,
( Enable INT0 )
16 0x40 ( INT0 ) LDI,
GIMSK 16 OUT,
( Setup buffer )
29 ( YH ) CLR,
28 ( YL ) SRAM_START 0xff AND LDI,
31 ( ZH ) CLR,
30 ( ZL ) SRAM_START 0xff AND LDI,
( Setup timer. We use the timer to clear up "processbit"
registers after 100us without a clock. This allows us to start
the next frame in a fresh state. at 1MHZ, no prescaling is
necessary. Each TCNT0 tick is already 1us long. )
16 0x01 ( CS00 ) LDI, ( no prescaler )
TCCR0B 16 OUT,
( init DDRB )
DDRB CP SBI,
PORTB LR CBI,
DDRB LR SBI,
SEI,
L1 LBL! ( loop )