mirror of
https://github.com/hsoft/collapseos.git
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136 lines
3.6 KiB
Forth
136 lines
3.6 KiB
Forth
( Receives keystrokes from PS/2 keyboard and send them to the
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'164. On the PS/2 side, it works the same way as the controller
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in the rc2014/ps2 recipe. However, in this case, what we have
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on the other side isn't a z80 bus, it's the one of the two
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controller ports of the SMS through a DB9 connector.
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The PS/2 related code is copied from rc2014/ps2 without much
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change. The only differences are that it pushes its data to a
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'164 instead of a '595 and that it synchronizes with the SMS
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with a SR latch, so we don't need PCINT. We can also afford to
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run at 1MHz instead of 8.
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*** Register Usage ***
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GPIOR0 flags:
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0 - when set, indicates that the DATA pin was high when we
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received a bit through INT0. When we receive a bit, we set
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flag T to indicate it.
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R16: tmp stuff
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R17: recv buffer. Whenever we receive a bit, we push it in
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there.
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R18: recv step:
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- 0: idle
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- 1: receiving data
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- 2: awaiting parity bit
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- 3: awaiting stop bit
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R19: Register used for parity computations and tmp value in
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some other places
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R20: data being sent to the '164
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Y: pointer to the memory location where the next scan code from
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ps/2 will be written.
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Z: pointer to the next scan code to push to the 595 )
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0x0060 CONSTANT SRAM_START
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0x015f CONSTANT RAMEND
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0x3d CONSTANT SPL
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0x3e CONSTANT SPH
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0x11 CONSTANT GPIOR0
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0x35 CONSTANT MCUCR
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0x33 CONSTANT TCCR0B
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0x3b CONSTANT GIMSK
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0x38 CONSTANT TIFR
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0x16 CONSTANT PINB
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0x17 CONSTANT DDRB
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0x18 CONSTANT PORTB
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2 CONSTANT CLK
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1 CONSTANT DATA
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3 CONSTANT CP
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0 CONSTANT LQ
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4 CONSTANT LR
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0x100-100 CONSTANT TIMER_INITVAL
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( We need a lot of labels in this program... )
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VARIABLE L5 VARIABLE L6 VARIABLE L7 VARIABLE L8
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H@ ORG !
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L1 FLBL, ( main )
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L2 FLBL, ( hdlINT0 )
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( Read DATA and set GPIOR0/0 if high. Then, set flag T.
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no SREG fiddling because no SREG-modifying instruction )
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L2 ' RJMP FLBL! ( hdlINT0 )
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PINB DATA SBIC,
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GPIOR0 0 SBI,
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SET,
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RETI,
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L1 ' RJMP FLBL! ( main )
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16 RAMEND 0xff AND LDI,
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SPL 16 OUT,
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16 RAMEND 8 RSHIFT LDI,
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SPH 16 OUT,
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( init variables )
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18 CLR,
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GPIOR0 18 OUT,
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( Setup int0
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INT0, falling edge )
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16 0x02 ( ISC01 ) LDI,
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MCUCR 16 OUT,
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( Enable INT0 )
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16 0x40 ( INT0 ) LDI,
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GIMSK 16 OUT,
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( Setup buffer )
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29 ( YH ) CLR,
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28 ( YL ) SRAM_START 0xff AND LDI,
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31 ( ZH ) CLR,
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30 ( ZL ) SRAM_START 0xff AND LDI,
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( Setup timer. We use the timer to clear up "processbit"
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registers after 100us without a clock. This allows us to start
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the next frame in a fresh state. at 1MHZ, no prescaling is
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necessary. Each TCNT0 tick is already 1us long. )
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16 0x01 ( CS00 ) LDI, ( no prescaler )
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TCCR0B 16 OUT,
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( init DDRB )
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DDRB CP SBI,
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PORTB LR CBI,
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DDRB LR SBI,
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SEI,
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L1 LBL! ( loop )
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L2 FLBL, ( BRTS processbit. flag T set? we have a bit to
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process )
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28 ( YL ) 30 ( ZL ) CP, ( if YL == ZL, buf is empty )
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L3 FLBL, ( BRNE sendTo164. YL != ZL? buf has data )
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( nothing to do. Before looping, let's check if our
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communication timer overflowed. )
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16 TIFR IN,
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16 1 ( TOV0 ) SBRC,
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L4 FLBL, ( RJMP processbitReset, timer0 overflow? reset )
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( Nothing to do for real. )
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L1 ' RJMP LBL, ( loop )
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( Process the data bit received in INT0 handler. )
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L2 ' BRTS FLBL! ( processbit )
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19 GPIOR0 IN, ( backup GPIOR0 before we reset T )
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19 0x1 ANDI, ( only keep the first flag )
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GPIOR0 0 CBI,
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CLT, ( ready to receive another bit )
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( We've received a bit. reset timer )
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L2 FLBL, ( RCALL resetTimer )
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( Which step are we at? )
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18 TST,
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L5 FLBL, ( BREQ processbits0 )
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18 1 CPI,
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L6 FLBL, ( BREQ processbits1 )
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18 2 CPI,
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L7 FLBL, ( BREQ processbits2 )
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( step 3: stop bit )
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18 CLR, ( happens in all cases )
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( DATA has to be set )
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19 TST, ( was DATA set? )
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L1 ' BREQ FLBL! ( loop, not set? error, don't push to buf )
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( push r17 to the buffer )
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