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Author SHA1 Message Date
Virgil Dupras
faa2576f83 CI: don't needlessly run tests twice
Verifying that forth.bin is stable is enough. Also, fix shebang.
2020-05-14 18:58:06 -04:00
Virgil Dupras
87b51a6261 By default, allocate about 0x100 bytes for PSP+RSP
During "make updatebootstrap", we use less than 0x20 bytes on the
PSP side and less than 0x40 bytes on the RSP one. 0x100 bytes ought
to be enough for anybody.
2020-05-14 18:41:09 -04:00
Virgil Dupras
bf289b0a67 z80a: de-variable-ize
Use straight VARIABLE instead of Z80MEM+. Initially, I used this
system to allow z80a to be embedded in a system binary, but now
I don't think it's worth it. Compiled, z80a is 2.5k. Sure, it's a
sizeable amount of RAM, but I think that even with it in RAM, I'll
manage a bootstrap within my most constrained machine, the SMS with
8K.
2020-05-14 15:29:22 -04:00
Virgil Dupras
3fbae082f4 Remove INTJUMP mechanism
Not worth the trouble. Easier to set jump in binary directly.
2020-05-14 15:13:16 -04:00
Virgil Dupras
a5269a1c7c Make blk use system RAM 2020-05-14 14:51:20 -04:00
Virgil Dupras
eec9549bde Make rdln use system RAM 2020-05-14 14:26:56 -04:00
23 changed files with 63 additions and 79 deletions

31
blk/081
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@ -1,17 +1,16 @@
RAMSTART FUTURE USES +55 (key) override RAMSTART FUTURE USES +3c BLK(*
+02 CURRENT +57 readln's variables +02 CURRENT +3e FUTURE USES
+04 HERE +59 blk's variables +04 HERE
+06 C<? +5b z80a's variables +06 C<? +51 CURRENTPTR
+08 C<* override +5d adev's variables +08 C<* override +53 (emit) override
+0a NLPTR +5f FUTURE USES +0a NLPTR +55 (key) override
+0c C<* +70 DRIVERS +0c C<* +57 FUTURE USES
+0e WORDBUF +80 RAMEND +0e WORDBUF
+2e BOOT C< PTR +2e BOOT C< PTR +5d adev's variables
+30 FUTURE USES +30 IN> +5f FUTURE USES
+4e INTJUMP +32 IN(* +70 DRIVERS
+51 CURRENTPTR +34 BLK@* +80 RAMEND
+53 (emit) override +36 BLK!*
+38 BLK>
+3a BLKDTY
(cont.) (cont.)

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@ -9,8 +9,8 @@ PARSEPTR holds routine address called on (parse)
C<* holds routine address called on C<. If the C<* override C<* holds routine address called on C<. If the C<* override
at 0x08 is nonzero, this routine is called instead. at 0x08 is nonzero, this routine is called instead.
IN> is the current position in IN(, which is the input buffer.
IN(* is a pointer to the input buffer, allocated at runtime.
(cont.) (cont.)

10
blk/083
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@ -7,10 +7,10 @@ WORDBUF is the buffer used by WORD
BOOT C< PTR is used when Forth boots from in-memory BOOT C< PTR is used when Forth boots from in-memory
source. See "Initialization sequence" below. source. See "Initialization sequence" below.
INTJUMP All RST offsets (well, not *all* at this moment, I
still have to free those slots...) in boot binaries are made to
jump to this address. If you use one of those slots for an
interrupt, write a jump to the appropriate offset in that RAM
location.
(cont.) (cont.)

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@ -7,10 +7,9 @@ for example), it can point elsewhere.
NLPTR points to an alternative routine for NL (by default, NLPTR points to an alternative routine for NL (by default,
CRLF). CRLF).
BLK* see B416.
FUTURE USES section is unused for now. FUTURE USES section is unused for now.
DRIVERS section is reserved for recipe-specific DRIVERS section is reserved for recipe-specific drivers.
drivers. Here is a list of known usages:
* 0x70-0x78: ACIA buffer pointers in RC2014 recipes.

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@ -1,2 +1 @@
1 LOAD+ Z80A$ 1 37 LOADR+
3 37 LOADR+

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@ -1,9 +1,6 @@
: Z80AMEM+ 0x5b RAM+ @ + ; VARIABLE ORG
: ORG 0 Z80AMEM+ ; VARIABLE BIN( 0 BIN( !
: BIN( 2 Z80AMEM+ ; VARIABLE L1 VARIABLE L2 VARIABLE L3 VARIABLE L4
: L1 4 Z80AMEM+ ; : L2 6 Z80AMEM+ ;
: L3 8 Z80AMEM+ ; : L4 10 Z80AMEM+ ;
: Z80A$ H@ 0x5b RAM+ ! 12 ALLOT 0 BIN( ! ;
: A 7 ; : B 0 ; : C 1 ; : D 2 ; : A 7 ; : B 0 ; : C 1 ; : D 2 ;
: E 3 ; : H 4 ; : L 5 ; : (HL) 6 ; : E 3 ; : H 4 ; : L 5 ; : (HL) 6 ;
: BC 0 ; : DE 1 ; : HL 2 ; : AF 3 ; : SP AF ; : BC 0 ; : DE 1 ; : HL 2 ; : AF 3 ; : SP AF ;

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@ -8,8 +8,8 @@ EXDEHL, JP(HL), NOP, ( 17, nativeWord )
0 JPnn, ( 1a, next ) 0 JPnn, ( 1d, chkPS ) 0 JPnn, ( 1a, next ) 0 JPnn, ( 1d, chkPS )
NOP, NOP, ( 20, numberWord ) NOP, NOP, ( 22, litWord ) NOP, NOP, ( 20, numberWord ) NOP, NOP, ( 22, litWord )
NOP, NOP, ( 24, addrWord ) NOP, NOP, ( 26, unused ) NOP, NOP, ( 24, addrWord ) NOP, NOP, ( 26, unused )
RAMSTART 0x4e + JPnn, ( 28, RST 28 ) 0 JPnn, ( RST 28 )
0 JPnn, ( 2b, doesWord ) NOP, NOP, ( 2e, unused ) 0 JPnn, ( 2b, doesWord ) NOP, NOP, ( 2e, unused )
RAMSTART 0x4e + JPnn, ( RST 30 ) 0 JPnn, ( RST 30 )
0 JPnn, ( 33, execute ) NOP, NOP, ( unused ) 0 JPnn, ( 33, execute ) NOP, NOP, ( unused )
RAMSTART 0x4e + JPnn, ( RST 38 ) 0 JPnn, ( RST 38 )

11
blk/416
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@ -1,13 +1,12 @@
: BLKMEM+ 0x59 RAM+ @ + ;
( n -- Fetches block n and write it to BLK( ) ( n -- Fetches block n and write it to BLK( )
: BLK@* 0 BLKMEM+ ; : BLK@* 0x34 RAM+ ;
( n -- Write back BLK( to storage at block n ) ( n -- Write back BLK( to storage at block n )
: BLK!* 2 BLKMEM+ ; : BLK!* 0x36 RAM+ ;
( Current blk pointer in ( ) ( Current blk pointer in ( )
: BLK> 4 BLKMEM+ ; : BLK> 0x38 RAM+ ;
( Whether buffer is dirty ) ( Whether buffer is dirty )
: BLKDTY 6 BLKMEM+ ; : BLKDTY 0x3a RAM+ ;
: BLK( 8 BLKMEM+ ; : BLK( 0x3c RAM+ @ ;
: BLK) BLK( 1024 + ; : BLK) BLK( 1024 + ;

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@ -1,7 +1,6 @@
: BLK$ : BLK$
H@ 0x59 RAM+ ! H@ 0x3c ( BLK(* ) RAM+ !
( 1024 for the block, 8 for variables ) 1024 ALLOT
1032 ALLOT
( LOAD detects end of block with ASCII EOT. This is why ( LOAD detects end of block with ASCII EOT. This is why
we write it there. EOT == 0x04 ) we write it there. EOT == 0x04 )
4 C, 4 C,

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@ -1,10 +1,9 @@
: RDLNMEM+ 0x57 RAM+ @ + ;
( current position in INBUF ) ( current position in INBUF )
: IN> 0 RDLNMEM+ ; : IN> 0x30 RAM+ ;
( points to INBUF ) ( points to INBUF )
: IN( 2 RDLNMEM+ ; : IN( 0x32 RAM+ @ ;
( points to INBUF's end ) ( points to INBUF's end )
: IN) 0x40 ( buffer size ) 2+ RDLNMEM+ ; : IN) 0x40 ( buffer size ) IN( + ;
( flush input buffer ) ( flush input buffer )
( set IN> to IN( and set IN> @ to null ) ( set IN> to IN( and set IN> @ to null )

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@ -1,10 +1,9 @@
( Initializes the readln subsystem ) ( Initializes the readln subsystem )
: RDLN$ : RDLN$
( 57 == rdln's memory ) H@ 0x32 ( IN(* ) RAM+ !
H@ 0x57 RAM+ !
( plus 2 for extra bytes after buffer: 1 for ( plus 2 for extra bytes after buffer: 1 for
the last typed 0x0a and one for the following NULL. ) the last typed 0x0a and one for the following NULL. )
IN) IN> - 2+ ALLOT IN) IN( - ALLOT
(infl) (infl)
['] RDLN< 0x0c RAM+ ! ['] RDLN< 0x0c RAM+ !
1 0x06 RAM+ ! ( 06 == C<? ) 1 0x06 RAM+ ! ( 06 == C<? )

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@ -1,4 +1,4 @@
CREATE ~ACIA (entry) ~ACIA ( Set RST 38 jump ) PC ORG @ 0x39 + !
AF PUSHqq, AF PUSHqq,
HL PUSHqq, HL PUSHqq,
DE PUSHqq, DE PUSHqq,

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@ -13,5 +13,3 @@
EI, EI,
RETI, RETI,

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@ -9,8 +9,5 @@
CR4:2 (101) - 8 bits + 1 stop bit CR4:2 (101) - 8 bits + 1 stop bit
CR1:0 (10) - Counter divide: 64 ) CR1:0 (10) - Counter divide: 64 )
0b10010110 [ ACIA_CTL LITN ] PC! 0b10010110 [ ACIA_CTL LITN ] PC!
( setup interrupt )
0xc3 0x4e RAM+ C! ( c3==JP, 4e==INTJUMP )
~ACIA 0x4f RAM+ !
(im1) ; (im1) ;

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@ -1,5 +1,5 @@
0x8000 CONSTANT RAMSTART 0x8000 CONSTANT RAMSTART
0xf000 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR 0xff00 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR
0x80 CONSTANT ACIA_CTL 0x81 CONSTANT ACIA_IO 0x80 CONSTANT ACIA_CTL 0x81 CONSTANT ACIA_IO
4 CONSTANT SDC_SPI 4 CONSTANT SDC_SPI
5 CONSTANT SDC_CSLOW 6 CONSTANT SDC_CSHIGH 5 CONSTANT SDC_CSLOW 6 CONSTANT SDC_CSHIGH

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@ -53,6 +53,7 @@ Machine* emul_init()
memset(m.mem, 0, 0x10000); memset(m.mem, 0, 0x10000);
m.ramstart = 0; m.ramstart = 0;
m.minsp = 0xffff; m.minsp = 0xffff;
m.maxix = 0;
for (int i=0; i<0x100; i++) { for (int i=0; i<0x100; i++) {
m.iord[i] = NULL; m.iord[i] = NULL;
m.iowr[i] = NULL; m.iowr[i] = NULL;
@ -74,6 +75,9 @@ bool emul_step()
if (newsp != 0 && newsp < m.minsp) { if (newsp != 0 && newsp < m.minsp) {
m.minsp = newsp; m.minsp = newsp;
} }
if (m.cpu.R1.wr.IX > m.maxix) {
m.maxix = m.cpu.R1.wr.IX;
}
return true; return true;
} else { } else {
return false; return false;
@ -116,4 +120,5 @@ void emul_memdump()
void emul_printdebug() void emul_printdebug()
{ {
fprintf(stderr, "Min SP: %04x\n", m.minsp); fprintf(stderr, "Min SP: %04x\n", m.minsp);
fprintf(stderr, "Max IX: %04x\n", m.maxix);
} }

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@ -14,6 +14,8 @@ typedef struct {
ushort ramstart; ushort ramstart;
// The minimum value reached by SP at any point during execution. // The minimum value reached by SP at any point during execution.
ushort minsp; ushort minsp;
// same principle for IX
ushort maxix;
// Array of 0x100 function pointers to IO read and write routines. Leave to // Array of 0x100 function pointers to IO read and write routines. Leave to
// NULL when IO port is unhandled. // NULL when IO port is unhandled.
IORD iord[0x100]; IORD iord[0x100];

Binary file not shown.

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@ -20,11 +20,6 @@ trouble of compiling defs to binary.
*/ */
// When DEBUG is set, stage1 is a core-less forth that works interactively.
// Useful for... debugging!
// By the way: there's a double-echo in stagedbg. It's normal. Don't panic.
//#define DEBUG
#define RAMSTART 0 #define RAMSTART 0
#define STDIO_PORT 0x00 #define STDIO_PORT 0x00
// To know which part of RAM to dump, we listen to port 2, which at the end of // To know which part of RAM to dump, we listen to port 2, which at the end of
@ -56,10 +51,6 @@ static uint8_t iord_stdio()
static void iowr_stdio(uint8_t val) static void iowr_stdio(uint8_t val)
{ {
// we don't output stdout in stage0 // we don't output stdout in stage0
#ifdef DEBUG
// ... unless we're in DEBUG mode!
putchar(val);
#endif
} }
static void iowr_here(uint8_t val) static void iowr_here(uint8_t val)
@ -101,12 +92,11 @@ int main(int argc, char *argv[])
while (running && emul_step()); while (running && emul_step());
#ifndef DEBUG
// We're done, now let's spit dict data // We're done, now let's spit dict data
for (int i=start_here; i<end_here; i++) { for (int i=start_here; i<end_here; i++) {
putchar(m->mem[i]); putchar(m->mem[i]);
} }
#endif emul_printdebug();
return 0; return 0;
} }

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@ -1,5 +1,5 @@
0xe800 CONSTANT RAMSTART 0xe800 CONSTANT RAMSTART
0xf000 CONSTANT RS_ADDR 0xff00 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR 0xfffa CONSTANT PS_ADDR
212 LOAD ( z80 assembler ) 212 LOAD ( z80 assembler )
262 LOAD ( xcomp ) 262 LOAD ( xcomp )

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@ -1,5 +1,5 @@
0x8000 CONSTANT RAMSTART 0x8000 CONSTANT RAMSTART
0xb000 CONSTANT RS_ADDR 0xbf00 CONSTANT RS_ADDR
0xbffa CONSTANT PS_ADDR 0xbffa CONSTANT PS_ADDR
RAMSTART 0x70 + CONSTANT LCD_MEM RAMSTART 0x70 + CONSTANT LCD_MEM
RAMSTART 0x72 + CONSTANT KBD_MEM RAMSTART 0x72 + CONSTANT KBD_MEM

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@ -1,4 +1,4 @@
0xf000 CONSTANT RS_ADDR 0xff00 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR 0xfffa CONSTANT PS_ADDR
RS_ADDR 0x80 - CONSTANT RAMSTART RS_ADDR 0x80 - CONSTANT RAMSTART
212 LOAD ( z80 assembler ) 212 LOAD ( z80 assembler )

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@ -1,4 +1,4 @@
#/bin/sh -e #!/bin/sh -e
git submodule init git submodule init
git submodule update git submodule update
@ -7,6 +7,8 @@ git clean -fxd
make -C emul make -C emul
make -C tests make -C tests
# let's try again with an updated boot bin # verify that forth.bin is stable
make -C emul updatebootstrap all cp emul/forth.bin ref.bin
make -C tests make -C emul updatebootstrap
cmp emul/forth.bin ref.bin
rm ref.bin