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aad6b5c2e5
...
8ca85abfbd
18
blk/671
18
blk/671
@ -1,15 +1,13 @@
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|||||||
( L1 LBL! .. L1 ' RJMP LBL, )
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( L1 LBL! .. L1 ' RJMP LBL, )
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||||||
: LBL! ( l -- ) PC SWAP ! ;
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: LBL! ( l -- ) PC SWAP ! ;
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||||||
: LBL, ( l op -- ) SWAP @ 1- SWAP EXECUTE A,, ;
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: LBL, ( l op -- ) SWAP @ 1- SWAP EXECUTE A,, ;
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||||||
: SKIP, PC 0 A,, ;
|
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||||||
: TO, ( opw pc )
|
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||||||
( warning: pc is a PC offset, not a mem addr! )
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||||||
2 * ORG @ + PC 1- H@ ( opw addr tgt hbkp )
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||||||
ROT HERE ! ( opw tgt hbkp ) SWAP ROT EXECUTE H@ ! ( hbkp )
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||||||
HERE ! ;
|
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||||||
( L1 FLBL, .. L1 ' RJMP FLBL! )
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( L1 FLBL, .. L1 ' RJMP FLBL! )
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||||||
: FLBL, ( l -- ) LBL! 0 A,, ;
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: FLBL, ( l -- ) LBL! 0 A,, ;
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||||||
: FLBL! ( l opw -- ) SWAP @ TO, ;
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: FLBL! ( l opw -- )
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||||||
: BEGIN, PC ; : AGAIN?, ( op ) SWAP 1- SWAP EXECUTE A,, ;
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( warning: l is a PC offset, not a mem addr! )
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||||||
: AGAIN, ['] RJMP AGAIN?, ;
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SWAP @ 2 * ORG @ + PC 1- H@ ( opw addr tgt hbkp )
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: IF, ['] BREQ SKIP, ; : THEN, TO, ;
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ROT HERE ! ( opw tgt hbkp ) SWAP ROT EXECUTE H@ ! ( hbkp )
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||||||
|
HERE ! ;
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||||||
|
: BEGIN, PC ;
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||||||
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: AGAIN, ( op ) SWAP 1- SWAP EXECUTE A,, ;
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||||||
|
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||||||
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8
blk/672
8
blk/672
@ -1,8 +0,0 @@
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|||||||
( Constant common to all AVR models )
|
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||||||
: R0 0 ; : R1 1 ; : R2 2 ; : R3 3 ; : R4 4 ; : R5 5 ; : R6 6 ;
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: R7 7 ; : R8 8 ; : R9 9 ; : R10 10 ; : R11 11 ; : R12 12 ;
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: R13 13 ; : R14 14 ; : R15 15 ; : R16 16 ; : R17 17 ;
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: R18 18 ; : R19 19 ; : R20 20 ; : R21 21 ; : R22 22 ;
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: R24 24 ; : R25 25 ; : R26 26 ; : R27 27 ; : R28 28 ;
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: R29 29 ; : R30 30 ; : R31 31 ; : XL R26 ; : XH R27 ;
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: YL R28 ; : YH R29 ; : ZL R30 ; : ZH R31 ;
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@ -67,31 +67,31 @@ SET,
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RETI,
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RETI,
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L1 ' RJMP FLBL! ( main )
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L1 ' RJMP FLBL! ( main )
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||||||
R16 RAMEND 0xff AND LDI,
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16 RAMEND 0xff AND LDI,
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||||||
SPL R16 OUT,
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SPL 16 OUT,
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||||||
R16 RAMEND 8 RSHIFT LDI,
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16 RAMEND 8 RSHIFT LDI,
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SPH R16 OUT,
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SPH 16 OUT,
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( init variables )
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( init variables )
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R18 CLR,
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18 CLR,
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GPIOR0 R18 OUT,
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GPIOR0 18 OUT,
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( Setup int0
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( Setup int0
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INT0, falling edge )
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INT0, falling edge )
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R16 0x02 ( ISC01 ) LDI,
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16 0x02 ( ISC01 ) LDI,
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MCUCR R16 OUT,
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MCUCR 16 OUT,
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( Enable INT0 )
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( Enable INT0 )
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R16 0x40 ( INT0 ) LDI,
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16 0x40 ( INT0 ) LDI,
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GIMSK R16 OUT,
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GIMSK 16 OUT,
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( Setup buffer )
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( Setup buffer )
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YH CLR,
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29 ( YH ) CLR,
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YL SRAM_START 0xff AND LDI,
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28 ( YL ) SRAM_START 0xff AND LDI,
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ZH CLR,
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31 ( ZH ) CLR,
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ZL SRAM_START 0xff AND LDI,
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30 ( ZL ) SRAM_START 0xff AND LDI,
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||||||
( Setup timer. We use the timer to clear up "processbit"
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( Setup timer. We use the timer to clear up "processbit"
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||||||
registers after 100us without a clock. This allows us to start
|
registers after 100us without a clock. This allows us to start
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||||||
the next frame in a fresh state. at 1MHZ, no prescaling is
|
the next frame in a fresh state. at 1MHZ, no prescaling is
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||||||
necessary. Each TCNT0 tick is already 1us long. )
|
necessary. Each TCNT0 tick is already 1us long. )
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R16 0x01 ( CS00 ) LDI, ( no prescaler )
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16 0x01 ( CS00 ) LDI, ( no prescaler )
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||||||
TCCR0B R16 OUT,
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TCCR0B 16 OUT,
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( init DDRB )
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( init DDRB )
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||||||
DDRB CP SBI,
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DDRB CP SBI,
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||||||
PORTB LR CBI,
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PORTB LR CBI,
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@ -101,20 +101,20 @@ SEI,
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|||||||
L1 LBL! ( loop )
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L1 LBL! ( loop )
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||||||
L2 FLBL, ( BRTS processbit. flag T set? we have a bit to
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L2 FLBL, ( BRTS processbit. flag T set? we have a bit to
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||||||
process )
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process )
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||||||
YL ZL CP, ( if YL == ZL, buf is empty )
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28 ( YL ) 30 ( ZL ) CP, ( if YL == ZL, buf is empty )
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||||||
L3 FLBL, ( BRNE sendTo164. YL != ZL? buf has data )
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L3 FLBL, ( BRNE sendTo164. YL != ZL? buf has data )
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||||||
( nothing to do. Before looping, let's check if our
|
( nothing to do. Before looping, let's check if our
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||||||
communication timer overflowed. )
|
communication timer overflowed. )
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||||||
R16 TIFR IN,
|
16 TIFR IN,
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||||||
R16 1 ( TOV0 ) SBRC,
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16 1 ( TOV0 ) SBRC,
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||||||
L4 FLBL, ( RJMP processbitReset, timer0 overflow? reset )
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L4 FLBL, ( RJMP processbitReset, timer0 overflow? reset )
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||||||
( Nothing to do for real. )
|
( Nothing to do for real. )
|
||||||
L1 ' RJMP LBL, ( loop )
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L1 ' RJMP LBL, ( loop )
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||||||
|
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||||||
( Process the data bit received in INT0 handler. )
|
( Process the data bit received in INT0 handler. )
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||||||
L2 ' BRTS FLBL! ( processbit )
|
L2 ' BRTS FLBL! ( processbit )
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||||||
R19 GPIOR0 IN, ( backup GPIOR0 before we reset T )
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19 GPIOR0 IN, ( backup GPIOR0 before we reset T )
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||||||
R19 0x1 ANDI, ( only keep the first flag )
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19 0x1 ANDI, ( only keep the first flag )
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||||||
GPIOR0 0 CBI,
|
GPIOR0 0 CBI,
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||||||
CLT, ( ready to receive another bit )
|
CLT, ( ready to receive another bit )
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||||||
|
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||||||
@ -122,31 +122,31 @@ CLT, ( ready to receive another bit )
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|||||||
L2 FLBL, ( RCALL resetTimer )
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L2 FLBL, ( RCALL resetTimer )
|
||||||
|
|
||||||
( Which step are we at? )
|
( Which step are we at? )
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||||||
R18 TST,
|
18 TST,
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||||||
L5 FLBL, ( BREQ processbits0 )
|
L5 FLBL, ( BREQ processbits0 )
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||||||
R18 1 CPI,
|
18 1 CPI,
|
||||||
L6 FLBL, ( BREQ processbits1 )
|
L6 FLBL, ( BREQ processbits1 )
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||||||
R18 2 CPI,
|
18 2 CPI,
|
||||||
L7 FLBL, ( BREQ processbits2 )
|
L7 FLBL, ( BREQ processbits2 )
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||||||
( step 3: stop bit )
|
( step 3: stop bit )
|
||||||
R18 CLR, ( happens in all cases )
|
18 CLR, ( happens in all cases )
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||||||
( DATA has to be set )
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( DATA has to be set )
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||||||
R19 TST, ( was DATA set? )
|
19 TST, ( was DATA set? )
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||||||
L1 ' BREQ LBL, ( loop, not set? error, don't push to buf )
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L1 ' BREQ LBL, ( loop, not set? error, don't push to buf )
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||||||
( push r17 to the buffer )
|
( push r17 to the buffer )
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||||||
Y+ R17 ST,
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Y+ 17 ST,
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||||||
L8 FLBL, ( RCALL checkBoundsY )
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L8 FLBL, ( RCALL checkBoundsY )
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||||||
L1 ' RJMP LBL,
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L1 ' RJMP LBL,
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||||||
|
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L5 ' BREQ FLBL! ( processbits0 )
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L5 ' BREQ FLBL! ( processbits0 )
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||||||
( step 0 - start bit )
|
( step 0 - start bit )
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||||||
( DATA has to be cleared )
|
( DATA has to be cleared )
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||||||
R19 TST, ( was DATA set? )
|
19 TST, ( was DATA set? )
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||||||
L1 ' BRNE LBL, ( loop. set? error. no need to do anything. keep
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L1 ' BRNE LBL, ( loop. set? error. no need to do anything. keep
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||||||
r18 as-is. )
|
r18 as-is. )
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||||||
( DATA is cleared. prepare r17 and r18 for step 1 )
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( DATA is cleared. prepare r17 and r18 for step 1 )
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R18 INC,
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18 INC,
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R17 0x80 LDI,
|
17 0x80 LDI,
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||||||
L1 ' RJMP LBL, ( loop )
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L1 ' RJMP LBL, ( loop )
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||||||
|
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||||||
L6 ' BREQ FLBL! ( processbits1 )
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L6 ' BREQ FLBL! ( processbits1 )
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||||||
@ -154,35 +154,35 @@ L6 ' BREQ FLBL! ( processbits1 )
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|||||||
We're about to rotate the carry flag into r17. Let's set it
|
We're about to rotate the carry flag into r17. Let's set it
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||||||
first depending on whether DATA is set. )
|
first depending on whether DATA is set. )
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||||||
CLC,
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CLC,
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||||||
R19 0 SBRC, ( skip if DATA is cleared )
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19 0 SBRC, ( skip if DATA is cleared )
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||||||
SEC,
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SEC,
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||||||
( Carry flag is set )
|
( Carry flag is set )
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||||||
R17 ROR,
|
17 ROR,
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||||||
( Good. now, are we finished rotating? If carry flag is set,
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( Good. now, are we finished rotating? If carry flag is set,
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||||||
it means that we've rotated in 8 bits. )
|
it means that we've rotated in 8 bits. )
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||||||
L1 ' BRCC LBL, ( loop )
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L1 ' BRCC LBL, ( loop )
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||||||
( We're finished, go to step 2 )
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( We're finished, go to step 2 )
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||||||
R18 INC,
|
18 INC,
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||||||
L1 ' RJMP LBL, ( loop )
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L1 ' RJMP LBL, ( loop )
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||||||
|
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||||||
L7 ' BREQ FLBL! ( processbits2 )
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L7 ' BREQ FLBL! ( processbits2 )
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||||||
( step 2 - parity bit )
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( step 2 - parity bit )
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||||||
R1 R19 MOV,
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1 19 MOV,
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||||||
R19 R17 MOV,
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19 17 MOV,
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L5 FLBL, ( RCALL checkParity )
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L5 FLBL, ( RCALL checkParity )
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R1 R16 CP,
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1 16 CP,
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L6 FLBL, ( BRNE processBitError, r1 != r16? wrong parity )
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L6 FLBL, ( BRNE processBitError, r1 != r16? wrong parity )
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||||||
R18 INC,
|
18 INC,
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||||||
L1 ' RJMP LBL, ( loop )
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L1 ' RJMP LBL, ( loop )
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||||||
|
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||||||
L6 ' BRNE FLBL! ( processBitError )
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L6 ' BRNE FLBL! ( processBitError )
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||||||
R18 CLR,
|
18 CLR,
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||||||
R19 0xfe LDI,
|
19 0xfe LDI,
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||||||
L6 FLBL, ( RCALL sendToPS2 )
|
L6 FLBL, ( RCALL sendToPS2 )
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||||||
L1 ' RJMP LBL, ( loop )
|
L1 ' RJMP LBL, ( loop )
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||||||
|
|
||||||
L4 ' RJMP FLBL! ( processbitReset )
|
L4 ' RJMP FLBL! ( processbitReset )
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||||||
R18 CLR,
|
18 CLR,
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||||||
L4 FLBL, ( RCALL resetTimer )
|
L4 FLBL, ( RCALL resetTimer )
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||||||
L1 ' RJMP LBL, ( loop )
|
L1 ' RJMP LBL, ( loop )
|
||||||
|
|
||||||
@ -197,20 +197,20 @@ L1 ' RJMP LBL, ( loop, even if we have something in the
|
|||||||
and processing it might mess things up. )
|
and processing it might mess things up. )
|
||||||
CLI,
|
CLI,
|
||||||
DDRB DATA SBI,
|
DDRB DATA SBI,
|
||||||
R20 Z+ LD,
|
20 Z+ LD,
|
||||||
L3 FLBL, ( RCALL checkBoundsZ )
|
L3 FLBL, ( RCALL checkBoundsZ )
|
||||||
R16 R8 LDI,
|
16 8 LDI,
|
||||||
|
|
||||||
BEGIN,
|
BEGIN,
|
||||||
PORTB DATA CBI,
|
PORTB DATA CBI,
|
||||||
R20 7 SBRC, ( if leftmost bit isn't cleared, set DATA high )
|
20 7 SBRC, ( if leftmost bit isn't cleared, set DATA high )
|
||||||
PORTB DATA SBI,
|
PORTB DATA SBI,
|
||||||
( toggle CP )
|
( toggle CP )
|
||||||
PORTB CP CBI,
|
PORTB CP CBI,
|
||||||
R20 LSL,
|
20 LSL,
|
||||||
PORTB CP SBI,
|
PORTB CP SBI,
|
||||||
R16 DEC,
|
16 DEC,
|
||||||
' BRNE AGAIN?, ( not zero yet? loop )
|
' BRNE AGAIN, ( not zero yet? loop )
|
||||||
( release PS/2 )
|
( release PS/2 )
|
||||||
DDRB DATA CBI,
|
DDRB DATA CBI,
|
||||||
SEI,
|
SEI,
|
||||||
@ -220,10 +220,10 @@ PORTB LR CBI,
|
|||||||
L1 ' RJMP LBL, ( loop )
|
L1 ' RJMP LBL, ( loop )
|
||||||
|
|
||||||
L2 ' RCALL FLBL! L4 ' RCALL FLBL! L2 LBL! ( resetTimer )
|
L2 ' RCALL FLBL! L4 ' RCALL FLBL! L2 LBL! ( resetTimer )
|
||||||
R16 TIMER_INITVAL LDI,
|
16 TIMER_INITVAL LDI,
|
||||||
TCNT0 R16 OUT,
|
TCNT0 16 OUT,
|
||||||
R16 0x02 ( TOV0 ) LDI,
|
16 0x02 ( TOV0 ) LDI,
|
||||||
TIFR R16 OUT,
|
TIFR 16 OUT,
|
||||||
RET,
|
RET,
|
||||||
|
|
||||||
L6 ' RCALL FLBL! ( sendToPS2 )
|
L6 ' RCALL FLBL! ( sendToPS2 )
|
||||||
@ -237,9 +237,9 @@ L2 ' RCALL LBL, ( resetTimer )
|
|||||||
|
|
||||||
( Wait until the timer overflows )
|
( Wait until the timer overflows )
|
||||||
BEGIN,
|
BEGIN,
|
||||||
R16 TIFR IN,
|
16 TIFR IN,
|
||||||
R16 1 ( TOV0 ) SBRS,
|
16 1 ( TOV0 ) SBRS,
|
||||||
AGAIN,
|
' RJMP AGAIN,
|
||||||
( Good, 100us passed. )
|
( Good, 100us passed. )
|
||||||
( Pull Data low, that's our start bit. )
|
( Pull Data low, that's our start bit. )
|
||||||
PORTB DATA CBI,
|
PORTB DATA CBI,
|
||||||
@ -251,42 +251,42 @@ DDRB DATA SBI,
|
|||||||
DDRB CLK CBI, ( Should be starting high now. )
|
DDRB CLK CBI, ( Should be starting high now. )
|
||||||
|
|
||||||
( We will do the next loop 8 times )
|
( We will do the next loop 8 times )
|
||||||
R16 8 LDI,
|
16 8 LDI,
|
||||||
( Let's remember initial r19 for parity )
|
( Let's remember initial r19 for parity )
|
||||||
R1 R19 MOV,
|
1 19 MOV,
|
||||||
|
|
||||||
BEGIN,
|
BEGIN,
|
||||||
( Wait for CLK to go low )
|
( Wait for CLK to go low )
|
||||||
BEGIN, PINB CLK SBIC, AGAIN,
|
BEGIN, PINB CLK SBIC, ' RJMP AGAIN,
|
||||||
( set up DATA )
|
( set up DATA )
|
||||||
PORTB DATA CBI,
|
PORTB DATA CBI,
|
||||||
R19 0 SBRC, ( skip if LSB is clear )
|
19 0 SBRC, ( skip if LSB is clear )
|
||||||
PORTB DATA SBI,
|
PORTB DATA SBI,
|
||||||
R19 LSR,
|
19 LSR,
|
||||||
( Wait for CLK to go high )
|
( Wait for CLK to go high )
|
||||||
BEGIN, PINB CLK SBIS, AGAIN,
|
BEGIN, PINB CLK SBIS, ' RJMP AGAIN,
|
||||||
16 DEC,
|
16 DEC,
|
||||||
' BRNE AGAIN?, ( not zero? loop )
|
' BRNE AGAIN, ( not zero? loop )
|
||||||
|
|
||||||
( Data was sent, CLK is high. Let's send parity )
|
( Data was sent, CLK is high. Let's send parity )
|
||||||
R19 R1 MOV, ( recall saved value )
|
19 1 MOV, ( recall saved value )
|
||||||
L6 FLBL, ( RCALL checkParity )
|
L6 FLBL, ( RCALL checkParity )
|
||||||
( Wait for CLK to go low )
|
( Wait for CLK to go low )
|
||||||
BEGIN, PINB CLK SBIC, AGAIN,
|
BEGIN, PINB CLK SBIC, ' RJMP AGAIN,
|
||||||
( set parity bit )
|
( set parity bit )
|
||||||
PORTB DATA CBI,
|
PORTB DATA CBI,
|
||||||
R16 0 SBRC, ( parity bit in r16 )
|
16 0 SBRC, ( parity bit in r16 )
|
||||||
PORTB DATA SBI,
|
PORTB DATA SBI,
|
||||||
( Wait for CLK to go high )
|
( Wait for CLK to go high )
|
||||||
BEGIN, PINB CLK SBIS, AGAIN,
|
BEGIN, PINB CLK SBIS, ' RJMP AGAIN,
|
||||||
( Wait for CLK to go low )
|
( Wait for CLK to go low )
|
||||||
BEGIN, PINB CLK SBIC, AGAIN,
|
BEGIN, PINB CLK SBIC, ' RJMP AGAIN,
|
||||||
( We can now release the DATA line )
|
( We can now release the DATA line )
|
||||||
DDRB DATA CBI,
|
DDRB DATA CBI,
|
||||||
( Wait for DATA to go low, that's our ACK )
|
( Wait for DATA to go low, that's our ACK )
|
||||||
BEGIN, PINB DATA SBIC, AGAIN,
|
BEGIN, PINB DATA SBIC, ' RJMP AGAIN,
|
||||||
( Wait for CLK to go low )
|
( Wait for CLK to go low )
|
||||||
BEGIN, PINB CLK SBIC, AGAIN,
|
BEGIN, PINB CLK SBIC, ' RJMP AGAIN,
|
||||||
( We're finished! Enable INT0, reset timer, everything back to
|
( We're finished! Enable INT0, reset timer, everything back to
|
||||||
normal! )
|
normal! )
|
||||||
L2 ' RCALL LBL, ( resetTimer )
|
L2 ' RCALL LBL, ( resetTimer )
|
||||||
@ -296,30 +296,4 @@ RET,
|
|||||||
|
|
||||||
L8 ' RCALL FLBL! ( checkBoundsY )
|
L8 ' RCALL FLBL! ( checkBoundsY )
|
||||||
( Check that Y is within bounds, reset to SRAM_START if not. )
|
( Check that Y is within bounds, reset to SRAM_START if not. )
|
||||||
YL TST,
|
28 ( YL ) TST,
|
||||||
IF, RET, ( not zero, nothing to do ) THEN,
|
|
||||||
( YL is zero. Reset Z )
|
|
||||||
YH CLR,
|
|
||||||
YL SRAM_START 0xff AND LDI,
|
|
||||||
RET,
|
|
||||||
|
|
||||||
L3 ' RCALL FLBL! ( checkBoundsZ )
|
|
||||||
( Check that Z is within bounds, reset to SRAM_START if not. )
|
|
||||||
ZL TST,
|
|
||||||
IF, RET, ( not zero, nothing to do ) THEN,
|
|
||||||
( ZL is zero. Reset Z )
|
|
||||||
ZH CLR,
|
|
||||||
ZL SRAM_START 0xff AND LDI,
|
|
||||||
RET,
|
|
||||||
|
|
||||||
L5 ' RCALL FLBL! L6 ' RCALL FLBL! ( checkParity )
|
|
||||||
( Counts the number of 1s in r19 and set r16 to 1 if there's an
|
|
||||||
even number of 1s, 0 if they're odd. )
|
|
||||||
R16 1 LDI,
|
|
||||||
BEGIN,
|
|
||||||
R19 LSR,
|
|
||||||
' BRCC SKIP, R16 INC, ( carry set? we had a 1 ) TO,
|
|
||||||
R19 TST, ( is r19 zero yet? )
|
|
||||||
' BRNE AGAIN?, ( no? loop )
|
|
||||||
R16 0x1 ANDI,
|
|
||||||
RET,
|
|
||||||
|
Loading…
Reference in New Issue
Block a user