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@ -178,17 +178,4 @@ arguments are separated by commas.
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To assemble an AVR assembler, use the `gluea.asm` file instead of the regular
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one.
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Note about AVR and PC: In most assemblers, arithmetics for instructions
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addresses have words (two bytes) as their basic unit because AVR instructions
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are either 16bit in length or 32bit in length. All addresses constants in
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upcodes are in words. However, in zasm's core logic, PC is in bytes (because z80
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upcodes can be 1 byte).
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The AVR assembler, of course, correctly translates byte PCs to words when
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writing upcodes, however, when you write your expressions, you need to remember
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to treat with bytes. For example, in a traditional AVR assembler, jumping to
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the instruction after the "foo" label would be "rjmp foo+1". In zasm, it's
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"rjmp foo+2". If your expression results in an odd number, the low bit of your
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number will be ignored.
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[libz80]: https://github.com/ggambetta/libz80
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@ -8,10 +8,11 @@
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; categories, and then alphabetically. Categories are ordered so that the 8bit
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; opcodes come first, then the 16bit ones. 0xff ends the chain
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instrNames:
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; Branching instructions. They are all shortcuts to BRBC/BRBS. These are not in
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; alphabetical order, but rather in "bit order". All "bit set" instructions
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; first (10th bit clear), then all "bit clear" ones (10th bit set). Inside this
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; order, they're then in "sss" order (bit number alias for BRBC/BRBS).
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; Branching instructions. They are all shortcuts to BRBC/BRBS. Their respective
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; bits are listed in instrBRBits. These are not in alphabetical order, but
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; rather in "bit order". All "bit set" instructions first (10th bit clear), then
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; all "bit clear" ones (10th bit set). Inside this order, they're then in "sss"
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; order (bit number alias for BRBC/BRBS)
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.db "BRCS", 0
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.db "BREQ", 0
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.db "BRMI", 0
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@ -31,7 +32,7 @@ instrNames:
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.equ I_BRBS 16
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.db "BRBS", 0
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.db "BRBC", 0
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; Rd(5) + Rr(5) (from here, instrUpMasks1)
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; Rd(5) + Rr(5)
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.equ I_ADC 18
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.db "ADC", 0
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.db "ADD", 0
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@ -46,21 +47,8 @@ instrNames:
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.db "OR", 0
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.db "SBC", 0
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.db "SUB", 0
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.equ I_ANDI 31
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.db "ANDI", 0
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.db "CPI", 0
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.db "LDI", 0
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.db "ORI", 0
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.db "SBCI", 0
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.db "SBR", 0
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.db "SUBI", 0
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.equ I_BLD 38
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.db "BLD", 0
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.db "BST", 0
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.db "SBRC", 0
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.db "SBRS", 0
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; no arg (from here, instrUpMasks2)
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.equ I_BREAK 42
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; no arg
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.equ I_BREAK 31
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.db "BREAK", 0
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.db "CLC", 0
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.db "CLH", 0
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@ -88,7 +76,7 @@ instrNames:
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.db "SLEEP", 0
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.db "WDR", 0
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; Rd(5)
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.equ I_ASR 68
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.equ I_ASR 57
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.db "ASR", 0
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.db "COM", 0
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.db "DEC", 0
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@ -123,20 +111,6 @@ instrUpMasks1:
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.db 0b00101000 ; OR
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.db 0b00001000 ; SBC
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.db 0b00011000 ; SUB
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; Rd(4) + K(8): XXXXKKKK ddddKKKK
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.db 0b01110000 ; ANDI
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.db 0b00110000 ; CPI
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.db 0b11100000 ; LDI
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.db 0b01100000 ; ORI
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.db 0b01000000 ; SBCI
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.db 0b01100000 ; SBR
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.db 0b01010000 ; SUBI
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; Rd(5) + bit: XXXXXXXd ddddXbbb: lonely bit in LSB is 0 in all cases, so we
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; ignore it.
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.db 0b11111000 ; BLD
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.db 0b11111010 ; BST
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.db 0b11111100 ; SBRC
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.db 0b11111110 ; SBRS
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; 16-bit constant masks associated with each instruction. In the same order as
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; in instrNames
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@ -184,6 +158,25 @@ instrUpMasks2:
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.db 0b10010100, 0b00000010 ; SWAP
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.db 0b10010010, 0b00000100 ; XCH
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instrBRBits:
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; 1st bit is 3rd bit of MSB and the other 3 are the lower bits of LSB
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.db 0b0000 ; BRCS
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.db 0b0001 ; BREQ
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.db 0b0010 ; BRMI
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.db 0b0011 ; BRVS
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.db 0b0100 ; BRLT
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.db 0b0101 ; BRHS
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.db 0b0110 ; BRTS
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.db 0b0111 ; BRIE
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.db 0b1000 ; BRCC
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.db 0b1001 ; BRNE
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.db 0b1010 ; BRPL
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.db 0b1011 ; BRVC
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.db 0b1100 ; BRGE
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.db 0b1101 ; BRHC
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.db 0b1110 ; BRTC
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.db 0b1111 ; BRID
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; Same signature as getInstID in instr.asm
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; Reads string in (HL) and returns the corresponding ID (I_*) in A. Sets Z if
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; there's a match.
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@ -222,29 +215,24 @@ getInstID:
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parseInstruction:
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; BC, during .spit, is ORred to the spitted opcode.
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ld bc, 0
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; Save Instr ID in D, which is less volatile than A. In almost all
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; cases, we fetch the opcode constant at the end of the processing.
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ld d, a
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cp I_ADC
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jp c, .BR
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cp I_ANDI
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jr c, .spitRd5Rr5
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cp I_BLD
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jr c, .spitRdK8
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cp I_BREAK
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jr c, .spitRdBit
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jr c, .spitRd5Rr5
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cp I_ASR
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jr c, .spitNoArg
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; spitRd5
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ld d, a ; save A for later
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call .readR5
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ret nz
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call .placeRd
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ld a, d ; restore A
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; continue to .spitNoArg
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.spitNoArg:
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call .getUp2
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jr .spit
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.spitRd5Rr5:
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ld d, a ; save A for later
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call .readR5
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ret nz
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call .placeRd
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@ -263,49 +251,10 @@ parseInstruction:
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rra \ rra \ rra
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or b
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ld b, a
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ld a, d ; restore A
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call .getUp1
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; now that's our MSB
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jr .spitMSB
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.spitRdK8:
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call .readR4
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ret nz
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call .placeRd
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call readComma
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call readWord
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call parseExpr
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ret nz
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ld a, c
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ld a, 0xff
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call .IX2A
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ret nz
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push af ; --> lvl 1
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; let's start with the 4 lower bits
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and 0xf
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or c
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; We now have our LSB in A. Let's spit it now.
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call ioPutB
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pop af ; <-- lvl 1
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; and now those high 4 bits
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and 0xf0
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rra \ rra \ rra \ rra
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ld b, a
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call .getUp1
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jr .spitMSB
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.spitRdBit:
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call .readR5
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ret nz
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call .placeRd
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call readComma
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ret nz
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call .readBit
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ret nz
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; LSB is in A and is ready to go
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call ioPutB
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call .getUp1
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jr .spitMSB
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.spit:
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; LSB is spit *before* MSB
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inc hl
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@ -380,8 +329,13 @@ parseInstruction:
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; upcode becomes 0b111101
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inc b
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.rdBRBS:
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call .readBit
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call readWord
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ret nz
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call parseExpr
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ld a, 7
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call .IX2A
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ret nz
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ld c, a
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call readComma
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ret nz
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jr .spitBR2
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@ -395,30 +349,19 @@ parseInstruction:
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ld c, a
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ret
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; Fetch a 8-bit upcode specified by instr index in D and set that upcode in HL
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; Fetch a 8-bit upcode specified by instr index in A and set that upcode in HL
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.getUp1:
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ld a, d
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sub I_ADC
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ld hl, instrUpMasks1
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jp addHL
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; Fetch a 16-bit upcode specified by instr index in D and set that upcode in HL
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; Fetch a 16-bit upcode specified by instr index in A and set that upcode in HL
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.getUp2:
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ld a, d
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sub I_BREAK
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sla a ; A * 2
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ld hl, instrUpMasks2
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jp addHL
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.readR4:
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call .readR5
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ret nz
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; has to be in the 16-31 range
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sub 0x10
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jp c, unsetZ
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cp a ; ensure Z
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ret
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; read a rXX argument and return register number in A.
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; Set Z for success.
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.readR5:
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@ -433,18 +376,6 @@ parseInstruction:
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ld a, 31
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jr .IX2A
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.readBit:
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call readWord
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ret nz
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call parseExpr
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ld a, 7
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call .IX2A
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ret nz
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or c
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ld c, a
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cp a ; ensure Z
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ret
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; Put IX's LSB into A and, additionally, ensure that the new value is <=
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; than what was previously in A.
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; Z for success.
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@ -7,5 +7,3 @@ breq bar
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asr r20
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bar:
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brbs 6, foo
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ori r22, 0x34+4
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sbrs r1, 3
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@ -1 +1 @@
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<08><><EFBFBD><EFBFBD><EFBFBD> <09>E<EFBFBD><45><EFBFBD>hc<13>
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<08><><EFBFBD><EFBFBD><EFBFBD> <09>E<EFBFBD><45><EFBFBD>
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