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mirror of https://github.com/hsoft/collapseos.git synced 2024-11-24 01:58:06 +11:00

Replace INITIAL_SP with PS_ADDR conf

Now I struggle to remember why I ever did things they way I did.
There must have been a reason...
This commit is contained in:
Virgil Dupras 2020-05-11 21:08:24 -04:00
parent 73482e7ea1
commit da371451cc
15 changed files with 40 additions and 37 deletions

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@ -1,6 +1,6 @@
STACK OVERFLOW PROTECTION: To avoid having to check for stack STACK OVERFLOW PROTECTION: To avoid having to check for stack
underflow after each pop operation (which can end up being underflow after each pop operation (which can end up being
prohibitive in terms of costs), we give ourselves a nice 6 prohibitive in terms of costs), PS_ADDR should be set to
bytes buffer. 6 bytes because we seldom have words requiring at least 6 bytes before its actual limit. 6 bytes because we
more than 3 items from the stack. Then, at each "exit" call we seldom have words requiring more than 3 items from the stack.
check for stack underflow. Then, at each "exit" call we check for stack underflow.

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@ -1,5 +1,4 @@
(cont.) RAMSTART FUTURE USES +55 (key) override
RAMSTART INITIAL_SP +55 (key) override
+02 CURRENT +57 readln's variables +02 CURRENT +57 readln's variables
+04 HERE +59 blk's variables +04 HERE +59 blk's variables
+06 C<? +5b z80a's variables +06 C<? +5b z80a's variables
@ -13,4 +12,5 @@ RAMSTART INITIAL_SP +55 (key) override
+53 (emit) override +53 (emit) override
(cont.) (cont.)

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@ -1,6 +1,3 @@
INITIAL_SP holds the initial Stack Pointer value so
that we know where to reset it on ABORT
CURRENT points to the last dict entry. CURRENT points to the last dict entry.
HERE points to current write offset. HERE points to current write offset.
@ -13,4 +10,7 @@ C<* holds routine address called on C<. If the C<* override
at 0x08 is nonzero, this routine is called instead. at 0x08 is nonzero, this routine is called instead.
(cont.) (cont.)

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blk/280
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@ -1,16 +1,16 @@
Z80 boot code Z80 boot code
This assembles the boot binary. It requires the Z80 assembler This assembles the boot binary. It requires the Z80 assembler
(B200) and cross compilation setup (B260). (B200) and cross compilation setup (B260). It also requires
these constants to be set:
On top of that, it requires RAMSTART to be defined as the RAMSTART: beginning address of RAM. This is where system
beginning address of RAM. This is where system variables are variables are placed. HERE is then placed at RAM+80 (ref B80).
placed. HERE is then placed at RAM+80 (ref B80).
We also need RS_ADDR to be set to the bottom address of the RS_ADDR: to be set to the bottom address of the Return Stack.
Return Stack.
RESERVED REGISTERS: At all times, IX points to RSP TOS and IY PS_ADDR: top address of the Parameter stack (PS grows down-
is IP. SP points to PSP TOS, but you can still use the stack\ wards). Allow space for stack underflow protection (B76).
in native code. you just have to make sure you've restored it
before "next". (cont.)
(cont.)

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blk/281
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@ -1,7 +1,12 @@
(cont.) STABLE ABI: The boot binary starts with a list of RESERVED REGISTERS: At all times, IX points to RSP TOS and IY
references. The address of these references have to stay to is IP. SP points to PSP TOS, but you can still use the stack\
those addresses. The rest of the Collapse OS code depend on it. in native code. you just have to make sure you've restored it
In fact, up until 0x67, the (?br) wordref, pretty much before "next".
everything has to stay put.
STABLE ABI: The boot binary starts with a list of references.
The address of these references have to stay to those addr-
esses. The rest of the Collapse OS code depend on it. In fact,
up until 0x67, the (?br) wordref, pretty much everything has
to stay put.
To assemble, run "282 LOAD". To assemble, run "282 LOAD".

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@ -3,8 +3,7 @@ L1 BSET 'B' A, 'O' A, 'O' A, 'T' A, 0 A,
PC ORG @ 1 + ! ( main ) PC ORG @ 1 + ! ( main )
( STACK OVERFLOW PROTECTION: See B76 ) ( STACK OVERFLOW PROTECTION: See B76 )
SP 0xfffa LDddnn, SP PS_ADDR LDddnn,
RAMSTART SP LD(nn)dd, ( RAM+00 == INITIAL_SP )
IX RS_ADDR LDddnn, IX RS_ADDR LDddnn,
( HERE begins at RAMEND ) ( HERE begins at RAMEND )
HL RAMSTART 0x80 + LDddnn, HL RAMSTART 0x80 + LDddnn,

10
blk/299
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@ -1,14 +1,10 @@
PC ORG @ 0x1e + ! ( chkPS ) PC ORG @ 0x1e + ! ( chkPS )
HL PUSHqq, HL PUSHqq,
RAMSTART LDHL(nn), ( RAM+00 == INITIAL_SP )
( We have the return address for this very call on the stack ( We have the return address for this very call on the stack
and protected registers. Let's compensate ) and protected registers. 4 - is to compensate that. )
HL DECss, HL PS_ADDR 4 - LDddnn,
HL DECss,
HL DECss,
HL DECss,
SP SUBHLss, SP SUBHLss,
HL POPqq, HL POPqq,
CNC RETcc, ( INITIAL_SP >= SP? good ) CNC RETcc, ( PS_ADDR >= SP? good )
JR, L2 BWR ( abortUnderflow-B298 ) JR, L2 BWR ( abortUnderflow-B298 )

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@ -9,7 +9,7 @@ CODE PICK
B (HL) LDrr, B (HL) LDrr,
( check PS range before returning ) ( check PS range before returning )
EXDEHL, EXDEHL,
RAMSTART LDHL(nn), ( RAM+00 == INITIAL_SP ) HL PS_ADDR LDddnn,
DE SUBHLss, DE SUBHLss,
CC L2 @ JPccnn, ( abortUnderflow-B298 ) CC L2 @ JPccnn, ( abortUnderflow-B298 )
BC PUSHqq, BC PUSHqq,

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@ -1,5 +1,5 @@
CODE S0 CODE S0
RAMSTART LDHL(nn), ( RAM+00 == INITIAL_SP ) HL PS_ADDR LDddnn,
HL PUSHqq, HL PUSHqq,
;CODE ;CODE

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@ -3,8 +3,7 @@ CODE BYE
;CODE ;CODE
CODE (resSP) CODE (resSP)
( INITIAL_SP == RAM+0 ) SP PS_ADDR LDddnn,
SP RAMSTART LDdd(nn),
;CODE ;CODE
CODE (resRS) CODE (resRS)

Binary file not shown.

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@ -1,5 +1,6 @@
0xe800 CONSTANT RAMSTART 0xe800 CONSTANT RAMSTART
0xf000 CONSTANT RS_ADDR 0xf000 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR
212 LOAD ( z80 assembler ) 212 LOAD ( z80 assembler )
262 LOAD ( xcomp ) 262 LOAD ( xcomp )
: CODE XCODE ; : CODE XCODE ;

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@ -1,5 +1,6 @@
0x8000 CONSTANT RAMSTART 0x8000 CONSTANT RAMSTART
0xf000 CONSTANT RS_ADDR 0xf000 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR
0x80 CONSTANT ACIA_CTL 0x80 CONSTANT ACIA_CTL
0x81 CONSTANT ACIA_IO 0x81 CONSTANT ACIA_IO
4 CONSTANT SDC_SPI 4 CONSTANT SDC_SPI

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@ -1,5 +1,6 @@
0x8000 CONSTANT RAMSTART 0x8000 CONSTANT RAMSTART
0xb000 CONSTANT RS_ADDR 0xb000 CONSTANT RS_ADDR
0xbffa CONSTANT PS_ADDR
RAMSTART 0x70 + CONSTANT LCD_MEM RAMSTART 0x70 + CONSTANT LCD_MEM
RAMSTART 0x72 + CONSTANT KBD_MEM RAMSTART 0x72 + CONSTANT KBD_MEM
0x01 CONSTANT KBD_PORT 0x01 CONSTANT KBD_PORT

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@ -1,4 +1,5 @@
0xf000 CONSTANT RS_ADDR 0xf000 CONSTANT RS_ADDR
0xfffa CONSTANT PS_ADDR
RS_ADDR 0x80 - CONSTANT RAMSTART RS_ADDR 0x80 - CONSTANT RAMSTART
212 LOAD ( z80 assembler ) 212 LOAD ( z80 assembler )
262 LOAD ( xcomp ) 262 LOAD ( xcomp )