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recipes/sms/kbd: use Collapse OS' AVR assembler
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@ -628,19 +628,19 @@ _parseArgs:
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_readBit:
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ld a, 7
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jr _readExpr
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jp _readExpr
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_readA6:
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ld a, 0x3f
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jr _readExpr
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jp _readExpr
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_readA5:
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ld a, 0x1f
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jr _readExpr
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jp _readExpr
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_readK8:
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ld a, 0xff
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jr _readExpr
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jp _readExpr
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_readDouble:
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push de
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@ -707,6 +707,12 @@ _readR5:
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push de
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ld a, (hl)
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call upcase
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cp 'X'
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jr z, .rdXYZ
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cp 'Y'
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jr z, .rdXYZ
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cp 'Z'
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jr z, .rdXYZ
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cp 'R'
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jr nz, .end ; not a register
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inc hl
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@ -717,6 +723,34 @@ _readR5:
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.end:
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pop de
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ret
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.rdXYZ:
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; First, let's get a base value, that is, (A-'X'+26)*2, because XL, our
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; lowest register, is equivalent to r26.
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sub 'X'
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rla ; no carry from sub
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add a, 26
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ld d, a ; store that
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inc hl
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ld a, (hl)
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call upcase
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cp 'H'
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jr nz, .skip1
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; second char is 'H'? our value is +1
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inc d
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jr .skip2
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.skip1:
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cp 'L'
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jr nz, .end ; not L either? then it's not good
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.skip2:
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; Good, we have our final value in D and we're almost sure it's a valid
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; register. Our only check left is that the 3rd char is a null.
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inc hl
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ld a, (hl)
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or a
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jr nz, .end
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; we're good
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ld a, d
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jr .end
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; Put DE's LSB into A and, additionally, ensure that the new value is <=
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; than what was previously in A.
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@ -1,12 +1,5 @@
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; *** CPU registers aliases ***
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.equ XH 27
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.equ XL 26
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.equ YH 29
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.equ YL 28
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.equ ZH 31
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.equ ZL 30
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.equ SREG_C 0 ; Carry Flag
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.equ SREG_Z 1 ; Zero Flag
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.equ SREG_N 2 ; Negative Flag
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@ -1,11 +1,13 @@
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PROGNAME = ps2ctl
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AVRDUDEMCU ?= t45
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AVRDUDEARGS ?= -c usbtiny -P usb
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TARGETS = $(PROGNAME).hex os.sms
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TARGETS = $(PROGNAME).bin os.sms
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BASEDIR = ../../..
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ZASM = $(BASEDIR)/emul/zasm/zasm
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KERNEL = $(BASEDIR)/kernel
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APPS = $(BASEDIR)/apps
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AVRA = $(BASEDIR)/emul/zasm/avra
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AVRINC = $(BASEDIR)/avr
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# Rules
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@ -14,14 +16,14 @@ APPS = $(BASEDIR)/apps
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all: $(TARGETS)
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@echo Done!
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send: $(PROGNAME).hex
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avrdude $(AVRDUDEARGS) -p $(AVRDUDEMCU) -U flash:w:$(PROGNAME).hex
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send: $(PROGNAME).bin
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avrdude $(AVRDUDEARGS) -p $(AVRDUDEMCU) -U flash:w:$(PROGNAME).bin
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$(PROGNAME).hex: $(PROGNAME).asm
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avra -o $@ $(PROGNAME).asm
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$(PROGNAME).bin: $(PROGNAME).asm
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$(AVRA) $(AVRINC) < $(PROGNAME).asm > $@
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os.sms: glue.asm
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$(ZASM) $(KERNEL) $(APPS) < glue.asm > $@
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clean:
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rm -f $(TARGETS) *.eep.hex *.obj os.bin
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rm -f $(TARGETS)
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@ -55,7 +55,6 @@ either the low or high bits.
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* 74xx157 (multiplexer)
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* A NOR SR-latch. I used a 4043.
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* Proto board, wires, IC sockets, etc.
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* [AVRA][avra]
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## Historical note
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@ -114,4 +113,3 @@ Just hook it on. I've tried it, it works.
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Did you get there? Feels pretty cool huh?
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[rc2014-ps2]: ../../rc2014/ps2
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[avra]: https://github.com/hsoft/avra
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@ -1,5 +1,3 @@
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.include "tn45def.inc"
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; Receives keystrokes from PS/2 keyboard and send them to the '164. On the PS/2
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; side, it works the same way as the controller in the rc2014/ps2 recipe.
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; However, in this case, what we have on the other side isn't a z80 bus, it's
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@ -30,17 +28,22 @@
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; written.
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; Z: pointer to the next scan code to push to the 595
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;
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.inc "avr.h"
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.inc "tn254585.h"
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.inc "tn45.h"
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; *** Constants ***
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.equ CLK = PINB2
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.equ DATA = PINB1
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.equ CP = PINB3
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.equ CLK 2 ; Port B
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.equ DATA 1 ; Port B
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.equ CP 3 ; Port B
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; SR-Latch's Q pin
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.equ LQ = PINB0
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.equ LQ 0 ; Port B
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; SR-Latch's R pin
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.equ LR = PINB4
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.equ LR 4 ; Port B
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; init value for TCNT0 so that overflow occurs in 100us
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.equ TIMER_INITVAL = 0x100-100
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.equ TIMER_INITVAL 0x100-100
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; *** Code ***
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@ -56,9 +59,9 @@ hdlINT0:
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reti
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main:
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ldi r16, low(RAMEND)
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ldi r16, RAMEND&0xff
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out SPL, r16
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ldi r16, high(RAMEND)
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ldi r16, RAMEND}8
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out SPH, r16
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; init variables
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@ -67,23 +70,23 @@ main:
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; Setup int0
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; INT0, falling edge
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ldi r16, (1<<ISC01)
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ldi r16, 0x02 ; ISC01
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out MCUCR, r16
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; Enable INT0
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ldi r16, (1<<INT0)
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ldi r16, 0x40 ; INT0
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out GIMSK, r16
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; Setup buffer
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clr YH
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ldi YL, low(SRAM_START)
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ldi YL, SRAM_START&0xff
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clr ZH
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ldi ZL, low(SRAM_START)
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ldi ZL, SRAM_START&0xff
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; Setup timer. We use the timer to clear up "processbit" registers after
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; 100us without a clock. This allows us to start the next frame in a
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; fresh state. at 1MHZ, no prescaling is necessary. Each TCNT0 tick is
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; already 1us long.
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ldi r16, (1<<CS00) ; no prescaler
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ldi r16, 0x01 ; CS00 - no prescaler
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out TCCR0B, r16
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; init DDRB
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@ -101,7 +104,7 @@ loop:
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; nothing to do. Before looping, let's check if our communication timer
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; overflowed.
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in r16, TIFR
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sbrc r16, TOV0
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sbrc r16, 1 ; TOV0
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rjmp processbitReset ; Timer0 overflow? reset processbit
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; Nothing to do for real.
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@ -220,7 +223,7 @@ sendTo164Loop:
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resetTimer:
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ldi r16, TIMER_INITVAL
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out TCNT0, r16
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ldi r16, (1<<TOV0)
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ldi r16, 0x02 ; TOV0
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out TIFR, r16
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ret
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@ -237,8 +240,8 @@ sendToPS2:
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; Wait until the timer overflows
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in r16, TIFR
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sbrs r16, TOV0
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rjmp PC-2
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sbrs r16, 1 ; TOV0
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rjmp $-4
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; Good, 100us passed.
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; Pull Data low, that's our start bit.
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@ -258,7 +261,7 @@ sendToPS2:
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sendToPS2Loop:
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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rjmp $-2
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; set up DATA
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cbi PORTB, DATA
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@ -268,7 +271,7 @@ sendToPS2Loop:
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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rjmp $-2
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dec r16
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brne sendToPS2Loop ; not zero? loop
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@ -279,7 +282,7 @@ sendToPS2Loop:
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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rjmp $-2
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; set parity bit
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cbi PORTB, DATA
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@ -288,22 +291,22 @@ sendToPS2Loop:
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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rjmp $-2
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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rjmp $-2
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; We can now release the DATA line
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cbi DDRB, DATA
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; Wait for DATA to go low. That's our ACK
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sbic PINB, DATA
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rjmp PC-1
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rjmp $-2
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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rjmp $-2
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; We're finished! Enable INT0, reset timer, everything back to normal!
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rcall resetTimer
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@ -314,21 +317,21 @@ sendToPS2Loop:
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; Check that Y is within bounds, reset to SRAM_START if not.
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checkBoundsY:
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tst YL
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breq PC+2
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breq $+4
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ret ; not zero, nothing to do
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; YL is zero. Reset Y
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clr YH
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ldi YL, low(SRAM_START)
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ldi YL, SRAM_START&0xff
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ret
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; Check that Z is within bounds, reset to SRAM_START if not.
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checkBoundsZ:
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tst ZL
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breq PC+2
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breq $+4
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ret ; not zero, nothing to do
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; ZL is zero. Reset Z
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clr ZH
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ldi ZL, low(SRAM_START)
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ldi ZL, SRAM_START&0xff
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ret
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; Counts the number of 1s in r19 and set r16 to 1 if there's an even number of
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@ -336,10 +339,10 @@ checkBoundsZ:
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checkParity:
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ldi r16, 1
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lsr r19
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brcc PC+2 ; Carry unset? skip next
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brcc $+4 ; Carry unset? skip next
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inc r16 ; Carry set? We had a 1
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tst r19 ; is r19 zero yet?
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brne checkParity+1 ; no? loop and skip first LDI
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brne checkParity+2 ; no? loop and skip first LDI
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andi r16, 0x1 ; Sets Z accordingly
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ret
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@ -24,3 +24,5 @@ jmp bar
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mov r6, r30
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lsl r3
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tst r12
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clr YH
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clr r29
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