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zasm: complete mnemonic argspecs harmonization

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This commit is contained in:
Virgil Dupras 2020-08-15 08:11:48 -04:00
parent a9ed8da0b2
commit 7ace3032ef
19 changed files with 43 additions and 43 deletions
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8
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@ -3,11 +3,11 @@ Z80 Assembler
201 Guide 208 Instructions list 201 Guide 208 Instructions list
212 Loader 213 Variables & consts 212 Loader 213 Variables & consts
215 Utils 216 OP1 215 Utils 216 OP1
218 OP1r 220 OP1qq 218 OP1r 220 OP1d
222 OP1rr 224 OP2 222 OP1rr 224 OP2
226 OP2n 228 OP2rn 226 OP2i 228 OP2ri
230 OP2br 232 OProt 230 OP2br 232 OProt
234 OP2r 236 OP2ss 234 OP2r 236 OP2d
238 OP3ddnn 240 OP3nn 238 OP3di 240 OP3i
242 Specials 246 Flow 242 Specials 246 Flow
249 Macros 249 Macros

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@ -1,5 +1,5 @@
( d n -- ) ( d i -- )
: OP3dn : OP3di
CREATE C, CREATE C,
DOES> DOES>
C@ ( d n op ) C@ ( d n op )
@ -8,4 +8,4 @@
OR A, OR A,
A,, A,,
; ;
0x01 OP3dn LDdn, 0x01 OP3di LDdi,

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@ -1,11 +1,11 @@
( n -- ) ( i -- )
: OP3n : OP3i
CREATE C, CREATE C,
DOES> DOES>
C@ A, C@ A,
A,, A,,
; ;
0xcd OP3n CALL, 0xcd OP3i CALL,
0xc3 OP3n JP, 0xc3 OP3i JP,
0x22 OP3n LD(n)HL, 0x2a OP3n LDHL(n), 0x22 OP3i LD(i)HL, 0x2a OP3i LDHL(i),
0x32 OP3n LD(i)A, 0x3a OP3n LDA(i), 0x32 OP3i LD(i)A, 0x3a OP3i LDA(i),

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@ -1,9 +1,9 @@
: LDd(n), ( d n -- ) : LDd(i), ( d i -- )
0xed A, 0xed A,
SWAP <<4 0x4b OR A, SWAP <<4 0x4b OR A,
A,, A,,
; ;
: LD(n)d, ( n d -- ) : LD(i)d, ( i d -- )
0xed A, 0xed A,
<<4 0x43 OR A, <<4 0x43 OR A,
A,, A,,

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@ -1,9 +1,9 @@
( Macros ) ( Macros )
( clear carry + SBC ) ( clear carry + SBC )
: SUBHLd, A ORr, SBCHLd, ; : SUBHLd, A ORr, SBCHLd, ;
: PUSH0, DE 0 LDdn, DE PUSH, ; : PUSH0, DE 0 LDdi, DE PUSH, ;
: PUSH1, DE 1 LDdn, DE PUSH, ; : PUSH1, DE 1 LDdi, DE PUSH, ;
: PUSHZ, DE 0 LDdn, IFZ, DE INCd, THEN, DE PUSH, ; : PUSHZ, DE 0 LDdi, IFZ, DE INCd, THEN, DE PUSH, ;
: PUSHA, D 0 LDri, E A LDrr, DE PUSH, ; : PUSHA, D 0 LDri, E A LDrr, DE PUSH, ;
: HLZ, A H LDrr, L ORr, ; : HLZ, A H LDrr, L ORr, ;
: DEZ, A D LDrr, E ORr, ; : DEZ, A D LDrr, E ORr, ;

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@ -1,13 +1,13 @@
PC ORG @ 1 + ! ( main ) PC ORG @ 1 + ! ( main )
SP PS_ADDR LDdn, IX RS_ADDR LDdn, SP PS_ADDR LDdi, IX RS_ADDR LDdi,
( LATEST is a label to the latest entry of the dict. It is ( LATEST is a label to the latest entry of the dict. It is
written at offset 0x08 by the process or person building written at offset 0x08 by the process or person building
Forth. ) Forth. )
BIN( @ 0x08 + LDHL(n), BIN( @ 0x08 + LDHL(i),
SYSVARS 0x02 ( CURRENT ) + LD(n)HL, SYSVARS 0x02 ( CURRENT ) + LD(i)HL,
HERESTART [IF] HERESTART [IF]
HL HERESTART LDdn, HL HERESTART LDdi,
[THEN] [THEN]
SYSVARS 0x04 + LD(n)HL, ( RAM+04 == HERE ) SYSVARS 0x04 + LD(i)HL, ( RAM+04 == HERE )
DE BIN( @ 0x04 ( BOOT ) + LDd(n), DE BIN( @ 0x04 ( BOOT ) + LDd(i),
JR, L1 FWR ( execute, B287 ) JR, L1 FWR ( execute, B287 )

4
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@ -6,8 +6,8 @@ lblnext BSET PC ORG @ 0x1b + ! ( next )
IX PUSH, EX(SP)HL, ( do EX to count the IX push in SP ) IX PUSH, EX(SP)HL, ( do EX to count the IX push in SP )
SP SUBHLd, HL POP, SP SUBHLd, HL POP,
IFNC, ( SP <= IX? overflow ) IFNC, ( SP <= IX? overflow )
SP PS_ADDR LDdn, IX RS_ADDR LDdn, SP PS_ADDR LDdi, IX RS_ADDR LDdi,
DE BIN( @ 0x13 ( oflw ) + LDd(n), DE BIN( @ 0x13 ( oflw ) + LDd(i),
JR, L2 FWR ( execute, B287 ) JR, L2 FWR ( execute, B287 )
THEN, THEN,
LDA(BC), E A LDrr, BC INCd, LDA(BC), E A LDrr, BC INCd,

4
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@ -1,5 +1,5 @@
lbluflw BSET ( abortUnderflow ) lbluflw BSET ( abortUnderflow )
DE BIN( @ 0x06 ( uflw ) + LDd(n), DE BIN( @ 0x06 ( uflw ) + LDd(i),
JR, lblexec BWR JR, lblexec BWR
lblchkPS BSET ( chkPS ) lblchkPS BSET ( chkPS )
( Note that you only need to call this in words that push ( Note that you only need to call this in words that push
@ -8,7 +8,7 @@ lblchkPS BSET ( chkPS )
EXX, EXX,
( We have the return address for this very call on the stack ( We have the return address for this very call on the stack
and protected registers. 2- is to compensate that. ) and protected registers. 2- is to compensate that. )
HL PS_ADDR 2- LDdn, HL PS_ADDR 2- LDdi,
SP SUBHLd, SP SUBHLd,
EXX, EXX,
CNC RETc, ( PS_ADDR >= SP? good ) CNC RETc, ( PS_ADDR >= SP? good )

2
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@ -8,7 +8,7 @@ CODE PICK EXX, ( protect BC )
B (HL) LDrr, B (HL) LDrr,
( check PS range before returning ) ( check PS range before returning )
EXDEHL, EXDEHL,
HL PS_ADDR LDdn, HL PS_ADDR LDdi,
DE SUBHLd, DE SUBHLd,
IFC, EXX, lbluflw @ JP, THEN, IFC, EXX, lbluflw @ JP, THEN,
BC PUSH, BC PUSH,

4
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@ -1,10 +1,10 @@
CODE S0 CODE S0
HL PS_ADDR LDdn, HL PS_ADDR LDdi,
HL PUSH, HL PUSH,
;CODE ;CODE
CODE 'S CODE 'S
HL 0 LDdn, HL 0 LDdi,
SP ADDHLd, SP ADDHLd,
HL PUSH, HL PUSH,
;CODE ;CODE

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@ -1,7 +1,7 @@
CODE * EXX, ( protect BC ) CODE * EXX, ( protect BC )
( DE * BC -> DE (high) and HL (low) ) ( DE * BC -> DE (high) and HL (low) )
DE POP, BC POP, chkPS, DE POP, BC POP, chkPS,
HL 0 LDdn, HL 0 LDdi,
A 0x10 LDri, A 0x10 LDri,
BEGIN, BEGIN,
HL ADDHLd, HL ADDHLd,

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@ -4,7 +4,7 @@
CODE /MOD EXX, ( protect BC ) CODE /MOD EXX, ( protect BC )
DE POP, BC POP, chkPS, DE POP, BC POP, chkPS,
A B LDrr, B 16 LDri, A B LDrr, B 16 LDri,
HL 0 LDdn, HL 0 LDdi,
BEGIN, BEGIN,
SCF, C RL, RLA, SCF, C RL, RLA,
HL ADCHLd, DE SBCHLd, HL ADCHLd, DE SBCHLd,

4
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@ -3,9 +3,9 @@ CODE BYE
;CODE ;CODE
CODE (resSP) CODE (resSP)
SP PS_ADDR LDdn, SP PS_ADDR LDdi,
;CODE ;CODE
CODE (resRS) CODE (resRS)
IX RS_ADDR LDdn, IX RS_ADDR LDdi,
;CODE ;CODE

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@ -3,7 +3,7 @@ CODE CMP
DE POP, DE POP,
chkPS, chkPS,
DE SUBHLd, DE SUBHLd,
DE 0 LDdn, DE 0 LDdi,
IFNZ, ( < or > ) IFNZ, ( < or > )
DE INCd, DE INCd,
IFNC, ( < ) IFNC, ( < )

2
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@ -7,6 +7,6 @@ CODE 0 PUSH0, ;CODE
CODE 1 PUSH1, ;CODE CODE 1 PUSH1, ;CODE
CODE -1 CODE -1
HL -1 LDdn, HL -1 LDdi,
HL PUSH, HL PUSH,
;CODE ;CODE

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@ -1,6 +1,6 @@
: LINES 24 ; : COLS 80 ; : LINES 24 ; : COLS 80 ;
CODE BYE CODE BYE
HL 0 LDdn, HL 0 LDdi,
A 0x16 LDri, ( @EXIT ) A 0x16 LDri, ( @EXIT )
0x28 RST, 0x28 RST,
CODE @DCSTAT ( drv -- f ) EXX, ( protect BC ) CODE @DCSTAT ( drv -- f ) EXX, ( protect BC )

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@ -3,7 +3,7 @@
0xff mask. If it was a 0x20, we put a 0x7f mask. ) 0xff mask. If it was a 0x20, we put a 0x7f mask. )
: @GET, : @GET,
A 0x03 LDri, ( @GET ) A 0x03 LDri, ( @GET )
DE COM_DRV_ADDR LDdn, DE COM_DRV_ADDR LDdi,
0x28 RST, JRNZ, L2 FWR ( maybeerror ) 0x28 RST, JRNZ, L2 FWR ( maybeerror )
A ORr, A ORr,
CZ RETc, ( Sending a straight NULL ends the comm. ) ; CZ RETc, ( Sending a straight NULL ends the comm. ) ;
@ -13,4 +13,4 @@
0x28 RST, JRNZ, L3 FWR ( error ) 0x28 RST, JRNZ, L3 FWR ( error )
A C LDrr, ; A C LDrr, ;
H@ ORG ! H@ ORG !
HL DEST_ADDR LDdn, ( cont. ) HL DEST_ADDR LDdi, ( cont. )

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@ -4,10 +4,10 @@
ACIA_CTL INAi, 0x01 ANDi, ( is ACIA rcv buf full? ) ACIA_CTL INAi, 0x01 ANDi, ( is ACIA rcv buf full? )
IFZ, ( no, abort ) AF POP, EI, RETI, THEN, IFZ, ( no, abort ) AF POP, EI, RETI, THEN,
HL PUSH, HL PUSH,
HL ACIAW> LDdn, A (HL) LDrr, HL ACIAW> LDdi, A (HL) LDrr,
HL DECd, (HL) CPr, ( W> == R> ? ) HL DECd, (HL) CPr, ( W> == R> ? )
IFNZ, ( buffer not full ) IFNZ, ( buffer not full )
( get wr ptr ) HL ACIA( LDd(n), ( get wr ptr ) HL ACIA( LDd(i),
L ADDr, IFC, H INCr, THEN, L A LDrr, L ADDr, IFC, H INCr, THEN, L A LDrr,
( fetch/write ) ACIA_IO INAi, (HL) A LDrr, ( fetch/write ) ACIA_IO INAi, (HL) A LDrr,
( advance W> ) ACIAW> LDA(i), A INCr, ( advance W> ) ACIAW> LDA(i), A INCr,

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@ -1,7 +1,7 @@
CODE _blank ( this is way too slow in Forth ) CODE _blank ( this is way too slow in Forth )
A XORr, VDP_CTLPORT OUTiA, A XORr, VDP_CTLPORT OUTiA,
A 0x40 LDri, VDP_CTLPORT OUTiA, A 0x40 LDri, VDP_CTLPORT OUTiA,
HL 0x4000 LDdn, HL 0x4000 LDdi,
BEGIN, BEGIN,
A XORr, VDP_DATAPORT OUTiA, A XORr, VDP_DATAPORT OUTiA,
HL DECd, HLZ, HL DECd, HLZ,