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rc2014: we're almost getting there...
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parent
435b4f452c
commit
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44
drv/acia.fs
44
drv/acia.fs
@ -24,44 +24,6 @@ ACIA_IO: IO port for the ACIA's data registers
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( This means that if W> == R>, buffer is full.
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If R>+1 == W>, buffer is empty. )
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(entry) ~ACIA
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AF PUSHqq,
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HL PUSHqq,
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DE PUSHqq,
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( Read our character from ACIA into our BUFIDX )
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ACIA_CTL INAn,
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0x01 ANDn, ( is ACIA rcv buf full? )
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JRZ, L2 FWR ( end, no, wrong interrupt cause. )
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ACIAW> @ LDHL(nn),
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( is it == to ACIAR>? )
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DE ACIAR> @ LDdd(nn),
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( carry cleared from ANDn above )
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DE SBCHLss,
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JRZ, L3 FWR ( end, buffer full )
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( buffer not full, let's write )
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ACIA_IO INAn,
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(HL) A LDrr,
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( advance W> )
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HL INCss,
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DE ACIAR) @ LDdd(nn),
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DE SUBHLss,
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JRNZ, L4 FWR ( skip )
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( end of buffer reached )
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ACIA( @ LDHL(nn),
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L4 FSET ( skip )
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ACIAW> @ LD(nn)HL,
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L3 FSET L2 FSET ( end )
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DE POPqq,
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HL POPqq,
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AF POPqq,
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EI,
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RETI,
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: ACIA$
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H@ DUP DUP ACIA( ! ACIAR> !
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1 + ACIAW> ! ( write index starts one position later )
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@ -76,9 +38,9 @@ L3 FSET L2 FSET ( end )
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0b10010110 ACIA_CTL PC!
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( setup interrupt )
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( 51 == INTJUMP )
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0xc3 0x51 RAM+ C! ( JP upcode )
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['] ~ACIA 0x52 RAM+ !
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( 4e == INTJUMP )
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0xc3 0x4e RAM+ C! ( JP upcode )
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['] ~ACIA 0x4f RAM+ !
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(im1)
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;
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43
drv/acia.z80
Normal file
43
drv/acia.z80
Normal file
@ -0,0 +1,43 @@
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( Save ACIA ports from conf )
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ACIA_CTL
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: ACIA_CTL [ LITN ] ;
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ACIA_IO
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: ACIA_IO [ LITN ] ;
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(entry) ~ACIA
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AF PUSHqq,
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HL PUSHqq,
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DE PUSHqq,
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( Read our character from ACIA into our BUFIDX )
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ACIA_CTL INAn,
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0x01 ANDn, ( is ACIA rcv buf full? )
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JRZ, L2 FWR ( end, no, wrong interrupt cause. )
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ACIAW> @ LDHL(nn),
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( is it == to ACIAR>? )
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DE ACIAR> @ LDdd(nn),
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( carry cleared from ANDn above )
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DE SBCHLss,
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JRZ, L3 FWR ( end, buffer full )
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( buffer not full, let's write )
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ACIA_IO INAn,
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(HL) A LDrr,
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( advance W> )
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HL INCss,
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DE ACIAR) @ LDdd(nn),
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DE SUBHLss,
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JRNZ, L4 FWR ( skip )
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( end of buffer reached )
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ACIA( @ LDHL(nn),
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L4 FSET ( skip )
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ACIAW> @ LD(nn)HL,
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L3 FSET L2 FSET ( end )
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DE POPqq,
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HL POPqq,
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AF POPqq,
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EI,
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RETI,
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@ -1,25 +1,31 @@
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TARGET = os.bin
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BASEDIR = ../..
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FDIR = $(BASEDIR)/emul/forth
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STAGE1 = $(FDIR)/stage1
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FORTH0 = $(FDIR)/forth0.bin
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FDIR = $(BASEDIR)/forth
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EDIR = $(BASEDIR)/emul/forth
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STAGE2 = $(EDIR)/stage2
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EMUL = $(BASEDIR)/emul/hw/rc2014/classic
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SRCS = core.fs str.fs parse.fs readln.fs fmt.fs
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PATHS = conf.fs \
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${SRCS:%=$(BASEDIR)/forth/%} \
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PATHS = pre.fs \
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$(FDIR)/core.fs \
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$(FDIR)/str.fs \
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$(FDIR)/parse.fs \
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$(BASEDIR)/drv/acia.fs \
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run.fs \
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$(FDIR)/stop.fs
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$(FDIR)/print.fs \
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run.fs
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SLATEST = $(BASEDIR)/tools/slatest
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STRIPFC = $(BASEDIR)/tools/stripfc
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.PHONY: all
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all: $(TARGET)
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$(TARGET): dict.bin $(FORTH0) $(SLATEST)
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cat $(FORTH0) dict.bin > $@
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$(TARGET): boot.bin z80c.bin $(SLATEST) $(PATHS)
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cat boot.bin z80c.bin > $@
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$(SLATEST) $@
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cat $(PATHS) | $(STRIPFC) >> $@
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dict.bin: conf.fs
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cat $(PATHS) | $(STAGE1) > $@
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z80c.bin: boot.bin
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cat conf.fs $(FDIR)/z80c.fs $(BASEDIR)/drv/acia.z80 $(FDIR)/icore.fs | $(STAGE2) | tee $@ > /dev/null
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boot.bin: conf.fs
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cat conf.fs $(FDIR)/boot.fs | $(STAGE2) | tee $@ > /dev/null
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$(SLATEST):
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$(MAKE) -C $(BASEDIR)/tools
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3
recipes/rc2014/pre.fs
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3
recipes/rc2014/pre.fs
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@ -0,0 +1,3 @@
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96 RAM+ HERE !
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HERE @ 256 /MOD 8 PC! 8 PC!
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CURRENT @ 256 /MOD 8 PC! 8 PC!
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@ -1 +1 @@
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: INIT 5 5 PC! BYE ACIA$ INTERPRET ;
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ACIA$ LIT< hello (print) BYE
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