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avra: make CLR work properly

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This commit is contained in:
Virgil Dupras 2019-12-15 16:43:32 -05:00
parent 20861767e6
commit 2652c81519
3 changed files with 11 additions and 3 deletions
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10
apps/zasm/avr.asm
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@ -129,6 +129,8 @@ instrNames:
; AVR's mnemonics has those args reversed for more consistency
; (destination is always the first arg). The goal of this flag is to
; allow this kind of syntactic sugar with minimal complexity.
;
; Bit 6: Second arg is a copy of the first
; In the same order as in instrNames
instrTbl:
@ -136,7 +138,7 @@ instrTbl:
.db 0x02, 0b00011100, 0x00 ; ADC
.db 0x02, 0b00001100, 0x00 ; ADD
.db 0x02, 0b00100000, 0x00 ; AND
.db 0x02, 0b00100100, 0x00 ; CLR
.db 0x41, 0b00100100, 0x00 ; CLR (Rr copies Rd)
.db 0x02, 0b00010100, 0x00 ; CP
.db 0x02, 0b00000100, 0x00 ; CPC
.db 0x02, 0b00010000, 0x00 ; CPSE
@ -291,6 +293,8 @@ parseInstruction:
; InstrID is E
bit 7, (ix)
call nz, .swapHL ; Bit 7 set, swap H and L again!
bit 6, (ix)
call nz, .cpHintoL ; Bit 6 set, copy H into L
ld a, e ; InstrID
cp I_ANDI
jr c, .spitRd5Rr5
@ -474,6 +478,10 @@ parseInstruction:
ld l, a
ret
.cpHintoL:
ld l, h
ret
; Argspecs: two bytes describing the arguments that are accepted. Possible
; values:
;

2
tools/tests/avra/blink_tn45.asm
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@ -25,7 +25,7 @@ main:
ori r16, 0x05 ; CS00 + CS02 = 1024 prescaler
out TCCR0B, r16
;clr r1
clr r1
loop:
in r16, TIFR ; TIFR0

2
tools/tests/avra/blink_tn45.expected
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@ -1 +1 @@
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