izaya/collapseos
1
0
Fork 0
mirror of https://github.com/hsoft/collapseos.git synced 2024-11-23 16:48:06 +11:00
Code Issues Releases Wiki Activity

Move SIO driver into RC2014 recipe

Browse Source
This commit is contained in:
Virgil Dupras 2020-08-16 09:31:02 -04:00
parent ab72a4f383
commit 007252e459
17 changed files with 83 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
blk/001
View File

@ -10,4 +10,3 @@ MASTER INDEX
620 Sega Master System Recipe
650 AVR assembler 730 8086 assembler
800 8086 boot code 830 PC/AT recipe
850 Zilog SIO driver

6
blk/580
View File

@ -3,6 +3,6 @@ RC2014 Recipe
Support code for the RC2014 recipe. Contains drivers for the
ACIA, SD card and AT28 EEPROM.
581 ACIA 590 AT28 EEPROM
595 SPI relay 600 SD card
618 Xcomp unit
581 ACIA 586 Zilog SIO driver
592 AT28 EEPROM 595 SPI relay
600 SD card 618 Xcomp unit

14
blk/584 Normal file
View File

@ -0,0 +1,14 @@
: (key)
( inc then fetch )
[ ACIAR> LITN ] C@ 1+ [ ACIA_BUFSZ 1- LITN ] AND
( As long as R> == W>-1, it means that buffer is empty )
BEGIN DUP [ ACIAW> LITN ] C@ = NOT UNTIL
DUP [ ACIA( LITN ] @ + C@ ( ridx c )
SWAP [ ACIAR> LITN ] C! ( c )
;
: (emit)
( As long at CTL bit 1 is low, we are transmitting. wait )
BEGIN [ ACIA_CTL LITN ] PC@ 0x02 AND UNTIL
( The way is clear, go! )
[ ACIA_IO LITN ] PC!
;

11
blk/585 Normal file
View File

@ -0,0 +1,11 @@
: ACIA$
H@ [ ACIA( LITN ] ! 0 [ ACIAR> LITN ] C!
1 [ ACIAW> LITN ] C! ( write index starts one pos later )
[ ACIA_BUFSZ LITN ] ALLOT
( setup ACIA
CR7 (1) - Receive Interrupt enabled
CR6:5 (00) - RTS low, transmit interrupt disabled.
CR4:2 (101) - 8 bits + 1 stop bit
CR1:0 (10) - Counter divide: 64 )
0b10010110 [ ACIA_CTL LITN ] PC!
(im1) ;

5
blk/586 Normal file
View File

@ -0,0 +1,5 @@
Zilog SIO driver
Declarations at B587
Driver load range at B588-B590

28
blk/587
View File

@ -1,14 +1,14 @@
: (key)
( inc then fetch )
[ ACIAR> LITN ] C@ 1+ [ ACIA_BUFSZ 1- LITN ] AND
( As long as R> == W>-1, it means that buffer is empty )
BEGIN DUP [ ACIAW> LITN ] C@ = NOT UNTIL
DUP [ ACIA( LITN ] @ + C@ ( ridx c )
SWAP [ ACIAR> LITN ] C! ( c )
;
: (emit)
( As long at CTL bit 1 is low, we are transmitting. wait )
BEGIN [ ACIA_CTL LITN ] PC@ 0x02 AND UNTIL
( The way is clear, go! )
[ ACIA_IO LITN ] PC!
;
0x80 CONSTANT SIO_ACTL 0x81 CONSTANT SIO_ADATA
0x82 CONSTANT SIO_BCTL 0x83 CONSTANT SIO_BDATA
0x20 CONSTANT SIO_BUFSZ ( SZ-1 must be a mask )
( Address in memory that can be used variables shared
with SIO native words. 4 bytes used. )
CREATE SIO_MEM SYSVARS 0x70 + ,
( Points to SIO buf )
: SIO( SIO_MEM @ 2+ ;
( Read buf idx Pre-inc )
: SIOR> SIO_MEM @ ;
( Write buf idx Post-inc )
: SIOW> SIO_MEM @ 1+ ;
( This means that if W> == R>, buffer is full.
If R>+1 == W>, buffer is empty. )

26
blk/588
View File

@ -1,11 +1,15 @@
: ACIA$
H@ [ ACIA( LITN ] ! 0 [ ACIAR> LITN ] C!
1 [ ACIAW> LITN ] C! ( write index starts one pos later )
[ ACIA_BUFSZ LITN ] ALLOT
( setup ACIA
CR7 (1) - Receive Interrupt enabled
CR6:5 (00) - RTS low, transmit interrupt disabled.
CR4:2 (101) - 8 bits + 1 stop bit
CR1:0 (10) - Counter divide: 64 )
0b10010110 [ ACIA_CTL LITN ] PC!
(im1) ;
( INT handler. Set RST 38 jump ) PC ORG @ 0x39 + !
AF PUSH, BEGIN,
SIO_ACTL INAi, ( RR0 ) 0x01 ANDi, ( is recv buf full? )
IFZ, ( nope, exit ) A 0x20 ( CMD 4 ) LDri, SIO_ACTL OUTiA,
AF POP, EI, RETI, THEN,
HL PUSH,
HL SIOW> LDdi, A (HL) LDrr,
HL DECd, (HL) CPr, ( W> == R> ? )
IFNZ, ( buffer not full )
( get wr ptr ) HL SIO( LDd(i),
L ADDr, IFC, H INCr, THEN, L A LDrr,
( fetch/write ) SIO_ADATA INAi, (HL) A LDrr,
( advance W> ) SIOW> LDA(i), A INCr,
SIO_BUFSZ 1- ANDi, SIOW> LD(i)A,
THEN, HL POP, JR, AGAIN,

0
blk/854 → blk/589
View File

18
blk/590
View File

@ -1,6 +1,12 @@
AT28 Driver
Write to an AT28 EEPROM while making sure that proper timing
is followed and verify data integrity.
Load with "591 LOAD"
: _ [ SIO_ACTL LITN ] PC! ;
: SIO$
H@ [ SIO( LITN ] ! 0 [ SIOR> LITN ] C!
1 [ SIOW> LITN ] C! ( write index starts one pos later )
[ SIO_BUFSZ LITN ] ALLOT
0x18 _ ( CMD3 )
0x24 _ ( CMD2/PTR4 ) 0b11000100 _ ( WR4/64x/1stop/nopar )
0x03 _ ( PTR3 ) 0b11000001 _ ( WR3/RXen/8char )
0x05 _ ( PTR5 ) 0b11001000 _ ( WR5/TXen/8char )
0x21 _ ( CMD2/PTR1 ) 0b00011000 _ ( WR1/Rx INT all chars )
(im1)
;

6
blk/592 Normal file
View File

@ -0,0 +1,6 @@
AT28 Driver
Write to an AT28 EEPROM while making sure that proper timing
is followed and verify data integrity.
Load with "593 LOAD"

0
blk/591 → blk/593
View File

2
blk/618
View File

@ -5,7 +5,7 @@ RS_ADDR 0x80 - CONSTANT SYSVARS
212 LOAD ( z80 assembler )
262 LOAD ( xcomp ) 282 LOAD ( boot.z80.decl )
270 LOAD ( xcomp overrides ) 283 335 LOADR ( boot.z80 )
353 LOAD ( xcomp core low ) 583 588 LOADR ( acia )
353 LOAD ( xcomp core low ) 583 585 LOADR ( acia )
380 LOAD ( xcomp core high )
(entry) _
( Update LATEST )

5
blk/850
View File

@ -1,5 +0,0 @@
Zilog SIO driver
Declarations at B851
Driver load range at B852-BXXX.

14
blk/851
View File

@ -1,14 +0,0 @@
0x80 CONSTANT SIO_ACTL 0x81 CONSTANT SIO_ADATA
0x82 CONSTANT SIO_BCTL 0x83 CONSTANT SIO_BDATA
0x20 CONSTANT SIO_BUFSZ ( SZ-1 must be a mask )
( Address in memory that can be used variables shared
with SIO native words. 4 bytes used. )
CREATE SIO_MEM SYSVARS 0x70 + ,
( Points to SIO buf )
: SIO( SIO_MEM @ 2+ ;
( Read buf idx Pre-inc )
: SIOR> SIO_MEM @ ;
( Write buf idx Post-inc )
: SIOW> SIO_MEM @ 1+ ;
( This means that if W> == R>, buffer is full.
If R>+1 == W>, buffer is empty. )

15
blk/852
View File

@ -1,15 +0,0 @@
( INT handler. Set RST 38 jump ) PC ORG @ 0x39 + !
AF PUSH, BEGIN,
SIO_ACTL INAi, ( RR0 ) 0x01 ANDi, ( is recv buf full? )
IFZ, ( nope, exit ) A 0x20 ( CMD 4 ) LDri, SIO_ACTL OUTiA,
AF POP, EI, RETI, THEN,
HL PUSH,
HL SIOW> LDdi, A (HL) LDrr,
HL DECd, (HL) CPr, ( W> == R> ? )
IFNZ, ( buffer not full )
( get wr ptr ) HL SIO( LDd(i),
L ADDr, IFC, H INCr, THEN, L A LDrr,
( fetch/write ) SIO_ADATA INAi, (HL) A LDrr,
( advance W> ) SIOW> LDA(i), A INCr,
SIO_BUFSZ 1- ANDi, SIOW> LD(i)A,
THEN, HL POP, JR, AGAIN,

12
blk/855
View File

@ -1,12 +0,0 @@
: _ [ SIO_ACTL LITN ] PC! ;
: SIO$
H@ [ SIO( LITN ] ! 0 [ SIOR> LITN ] C!
1 [ SIOW> LITN ] C! ( write index starts one pos later )
[ SIO_BUFSZ LITN ] ALLOT
0x18 _ ( CMD3 )
0x24 _ ( CMD2/PTR4 ) 0b11000100 _ ( WR4/64x/1stop/nopar )
0x03 _ ( PTR3 ) 0b11000001 _ ( WR3/RXen/8char )
0x05 _ ( PTR5 ) 0b11001000 _ ( WR5/TXen/8char )
0x21 _ ( CMD2/PTR1 ) 0b00011000 _ ( WR1/Rx INT all chars )
(im1)
;

4
recipes/rc2014/eeprom/README.md
View File

@ -35,12 +35,12 @@ I don't think you need a schematic. It's really simple.
### Building the binary
The binary from the base recipe has almost all it needs to write to EEPROM. The
only thing it needs is the AT28 driver from B590. You could add it to the
only thing it needs is the AT28 driver from B592. You could add it to the
`xcomp` unit and rebuild, but the driver is so tiny, you're probably better off
loading it at runtime.
If your system has mass storage, it's as easy as a LOAD. If it doesn't, you
can use `/tools/exec` to send `blk/591` to the RC2014.
can use `/tools/exec` to send `blk/593` to the RC2014.
## Writing contents to the AT28