2020-04-05 07:07:35 +10:00
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( Save ACIA conf )
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2020-04-05 01:31:22 +11:00
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ACIA_CTL
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: ACIA_CTL [ LITN ] ;
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ACIA_IO
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: ACIA_IO [ LITN ] ;
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2020-04-05 07:07:35 +10:00
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( Points to ACIA buf )
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: ACIA( [ ACIA_MEM 4 + LITN ] ;
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( Points to ACIA buf end )
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: ACIA) [ ACIA_MEM 6 + LITN ] ;
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( Read buf pointer. Pre-inc )
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: ACIAR> [ ACIA_MEM LITN ] ;
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( Write buf pointer. Post-inc )
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: ACIAW> [ ACIA_MEM 2 + LITN ] ;
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( This means that if W> == R>, buffer is full.
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If R>+1 == W>, buffer is empty. )
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2020-04-05 01:31:22 +11:00
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(entry) ~ACIA
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AF PUSHqq,
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HL PUSHqq,
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DE PUSHqq,
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( Read our character from ACIA into our BUFIDX )
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ACIA_CTL INAn,
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0x01 ANDn, ( is ACIA rcv buf full? )
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JRZ, L2 FWR ( end, no, wrong interrupt cause. )
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2020-04-05 07:07:35 +10:00
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ACIAW> LDHL(nn),
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2020-04-05 01:31:22 +11:00
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( is it == to ACIAR>? )
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2020-04-05 07:07:35 +10:00
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DE ACIAR> LDdd(nn),
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2020-04-05 01:31:22 +11:00
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( carry cleared from ANDn above )
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DE SBCHLss,
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JRZ, L3 FWR ( end, buffer full )
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2020-04-05 07:07:35 +10:00
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DE ADDHLss, ( restore ACIAW> )
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2020-04-05 01:31:22 +11:00
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( buffer not full, let's write )
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ACIA_IO INAn,
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(HL) A LDrr,
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( advance W> )
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HL INCss,
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2020-04-05 07:07:35 +10:00
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ACIAW> LD(nn)HL,
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DE ACIA) @ LDdd(nn),
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2020-04-05 01:31:22 +11:00
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DE SUBHLss,
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JRNZ, L4 FWR ( skip )
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( end of buffer reached )
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ACIA( @ LDHL(nn),
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2020-04-05 07:07:35 +10:00
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ACIAW> LD(nn)HL,
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2020-04-05 01:31:22 +11:00
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L4 FSET ( skip )
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L3 FSET L2 FSET ( end )
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DE POPqq,
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HL POPqq,
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AF POPqq,
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EI,
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RETI,
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