izaya/collapseos
1
0
Fork 0
mirror of https://github.com/hsoft/collapseos.git synced 2024-11-27 22:38:05 +11:00
Code Issues Releases Wiki Activity
3615944ffa
collapseos/arch/z80/sms/blk/625

17 lines
696 B
Plaintext
Raw Normal View History

sms: simplify and solidify ports-related drivers Add _TRA!, _THA!, _TRB!, _THB! routines to easily handle those pins' value without stepping on other pins like the drivers previously did. For SDC driver, it's going to be important soon because it turns out that I can't get away with "always on" CS, so I'll need a scheme where it's important that TH/TR pins have stable values.
2020-11-03 10:53:57 +11:00
( Routines for interacting with SMS controller ports.
sms: CPORT_CTL is write-only! why did I think that I could read from it?
2020-11-09 00:43:24 +11:00
Requires CPORT_MEM, CPORT_CTL, CPORT_D1 and CPORT_D2 to be
defined. CPORT_MEM is a 1 byte buffer for CPORT_CTL. The last
3 consts will usually be 0x3f, 0xdc, 0xdd. )
sms: simplify and solidify ports-related drivers Add _TRA!, _THA!, _TRB!, _THB! routines to easily handle those pins' value without stepping on other pins like the drivers previously did. For SDC driver, it's going to be important soon because it turns out that I can't get away with "always on" CS, so I'll need a scheme where it's important that TH/TR pins have stable values.
2020-11-03 10:53:57 +11:00
( mode -- set TR pin on mode a on:
0= output low 1=output high 2=input )
CODE _TRA! HL POP, chkPS, ( B0 -> B4, B1 -> B0 )
L RR, RLA, RLA, RLA, RLA, L RR, RLA,
sms: CPORT_CTL is write-only! why did I think that I could read from it?
2020-11-09 00:43:24 +11:00
0x11 ANDi, L A LDrr, CPORT_MEM LDA(i),
0xee ANDi, L ORr, CPORT_CTL OUTiA, CPORT_MEM LD(i)A,
sms: simplify and solidify ports-related drivers Add _TRA!, _THA!, _TRB!, _THB! routines to easily handle those pins' value without stepping on other pins like the drivers previously did. For SDC driver, it's going to be important soon because it turns out that I can't get away with "always on" CS, so I'll need a scheme where it's important that TH/TR pins have stable values.
2020-11-03 10:53:57 +11:00
;CODE
CODE _THA! HL POP, chkPS, ( B0 -> B5, B1 -> B1 )
L RR, RLA, RLA, RLA, RLA, L RR, RLA, RLA,
sms: CPORT_CTL is write-only! why did I think that I could read from it?
2020-11-09 00:43:24 +11:00
0x22 ANDi, L A LDrr, CPORT_MEM LDA(i),
0xdd ANDi, L ORr, CPORT_CTL OUTiA, CPORT_MEM LD(i)A,
sms: simplify and solidify ports-related drivers Add _TRA!, _THA!, _TRB!, _THB! routines to easily handle those pins' value without stepping on other pins like the drivers previously did. For SDC driver, it's going to be important soon because it turns out that I can't get away with "always on" CS, so I'll need a scheme where it's important that TH/TR pins have stable values.
2020-11-03 10:53:57 +11:00
;CODE
Reference in New Issue Copy Permalink