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https://github.com/hsoft/collapseos.git
synced 2024-11-30 20:08:06 +11:00
d09de0a0d3
In the beginning of Collapse OS' Forth version, the readline sub- system was optional. This is why we had this separate RDLN$ routine and that the input buffer was allocated at boot time. It's been a while since the RDLN system has been made mandatory, but we still paid the complexity tax of this separation. Not anymore.
105 lines
3.7 KiB
Forth
105 lines
3.7 KiB
Forth
( ----- 600 )
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601 MC6850 driver 606 Zilog SIO driver
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615 SPI relay 619 Xcomp unit
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( ----- 601 )
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( MC6850 Driver. Load range B601-B603. Requires:
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6850_CTL for control register
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6850_IO for data register.
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CTL numbers used: 0x16 = no interrupt, 8bit words, 1 stop bit
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64x divide. 0x56 = RTS high )
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: _rts 0x16 ( RTS low ) [ 6850_CTL LITN ] PC! ;
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: _rts^ 0x56 ( RTS high ) [ 6850_CTL LITN ] PC! ;
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: 6850<? ( -- c? f )
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[ 6850_CTL LITN ] PC@ 1 AND ( is rcv buff full ? )
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NOT IF ( RTS low, then wait 1ms and try again )
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_rts 10 TICKS ( 1ms ) _rts^
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[ 6850_CTL LITN ] PC@ 1 AND ( is rcv buff full ? )
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NOT IF 0 EXIT THEN
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THEN [ 6850_IO LITN ] PC@ ( c ) 1 ( f ) ;
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( ----- 602 )
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CODE 6850>
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HL POP, chkPS,
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BEGIN,
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6850_CTL INAi, 0x02 ANDi, ( are we transmitting? )
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JRZ, ( yes, loop ) AGAIN,
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A L LDrr, 6850_IO OUTiA,
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;CODE
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( ----- 603 )
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: (key?) 6850<? ;
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: (emit) 6850> ;
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: 6850$ 0x56 ( RTS high ) [ 6850_CTL LITN ] PC! ;
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( ----- 605 )
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( Zilog SIO driver. Load range B605-607. Requires:
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SIOA_CTL for ch A control register
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SIOA_DATA for ch A data register
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SIOB_CTL for ch B control register
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SIOB_DATA for ch B data register )
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: _<? ( io ctl -- c? f )
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DUP ( io ctl ctl ) PC@ 1 AND ( is rcv buff full ? )
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NOT IF ( io ctl )
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0x05 ( PTR5 ) OVER PC! 0b01101000 OVER PC! ( RTS low )
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10 TICKS ( 1ms )
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0x05 ( PTR5 ) OVER PC! 0b01101010 OVER PC! ( RTS high )
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PC@ 1 AND ( is rcv buff full ? )
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NOT IF DROP 0 ( f ) EXIT THEN
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ELSE DROP THEN ( io ) PC@ ( c ) 1 ( f ) ;
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: SIOA<? [ SIOA_DATA LITN SIOA_CTL LITN ] _<? ;
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( ----- 606 )
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CODE SIOA>
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HL POP, chkPS,
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BEGIN,
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SIOA_CTL INAi, 0x04 ANDi, ( are we transmitting? )
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JRZ, ( yes, loop ) AGAIN,
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A L LDrr, SIOA_DATA OUTiA,
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;CODE
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CREATE _ ( init data ) 0x18 C, ( CMD3 )
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0x24 C, ( CMD2/PTR4 ) 0b11000100 C, ( WR4/64x/1stop/nopar )
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0x03 C, ( PTR3 ) 0b11000001 C, ( WR3/RXen/8char )
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0x05 C, ( PTR5 ) 0b01101010 C, ( WR5/TXen/8char/RTS )
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0x21 C, ( CMD2/PTR1 ) 0 C, ( WR1/Rx no INT )
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: SIOA$ 9 0 DO _ I + C@ [ SIOA_CTL LITN ] PC! LOOP ;
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( ----- 607 )
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: SIOB<? [ SIOB_DATA LITN SIOB_CTL LITN ] _<? ;
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CODE SIOB>
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HL POP, chkPS,
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BEGIN,
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SIOB_CTL INAi, 0x04 ANDi, ( are we transmitting? )
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JRZ, ( yes, loop ) AGAIN,
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A L LDrr, SIOB_DATA OUTiA,
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;CODE
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: SIOB$ 9 0 DO _ I + C@ [ SIOB_CTL LITN ] PC! LOOP ;
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( ----- 619 )
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( RC2014 classic with MC6850 )
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0xff00 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR
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RS_ADDR 0xa0 - CONSTANT SYSVARS
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0x8000 CONSTANT HERESTART
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0x80 CONSTANT 6850_CTL 0x81 CONSTANT 6850_IO
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4 CONSTANT SPI_DATA 5 CONSTANT SPI_CTL 1 CONSTANT SDC_DEVID
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5 LOAD ( z80 assembler )
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262 LOAD ( xcomp ) 282 LOAD ( boot.z80.decl )
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270 LOAD ( xcomp overrides ) 283 335 LOADR ( boot.z80 )
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353 LOAD ( xcomp core low ) 601 603 LOADR ( MC6850 )
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419 LOAD ( SPI relay ) 423 436 LOADR ( SD Card )
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400 LOAD ( AT28 )
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390 LOAD ( xcomp core high )
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(entry) _
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PC ORG @ 8 + ! ( Update LATEST )
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," 6850$ BLK$ " EOT,
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( ----- 620 )
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( RC2014 classic with SIO )
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0xff00 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR
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RS_ADDR 0xa0 - CONSTANT SYSVARS
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0x8000 CONSTANT HERESTART
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0x80 CONSTANT SIOA_CTL 0x81 CONSTANT SIOA_DATA
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0x82 CONSTANT SIOB_CTL 0x83 CONSTANT SIOB_DATA
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4 CONSTANT SPI_DATA 5 CONSTANT SPI_CTL 1 CONSTANT SDC_DEVID
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5 LOAD ( z80 assembler )
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262 LOAD ( xcomp ) 282 LOAD ( boot.z80.decl )
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270 LOAD ( xcomp overrides ) 283 335 LOADR ( boot.z80 )
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353 LOAD ( xcomp core low ) 605 607 LOADR ( SIO )
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419 LOAD ( SPI relay ) 423 436 LOADR ( SD Card )
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400 LOAD ( AT28 ) : (key?) SIOA<? ; : (emit) SIOA> ;
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390 LOAD ( xcomp core high )
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(entry) _ PC ORG @ 8 + ! ( Update LATEST )
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," SIOA$ BLK$ " EOT,
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