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344 lines
9.6 KiB
NASM
344 lines
9.6 KiB
NASM
; This is a copy of my seg7multiplex main program, translated for zasm.
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; The output of zasm was verified against avra's.
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; 7-segments multiplexer for an ATtiny45
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;
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; Register usage
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; R0: Digit on AFF1 (rightmost, QH on the SR)
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; R1: Digit on AFF2 (QG on the SR)
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; R2: Digit on AFF3 (QF on the SR)
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; R3: Digit on AFF4 (leftmost, QE on the SR)
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; R5: always zero
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; R6: generic tmp value
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; R16: generic tmp value
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; R18: value to send to the SR. cleared at every SENDSR call
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; in input mode, holds the input buffer
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; R30: (low Z) current digit being refreshed. cycles from 0 to 3
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;
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; Flags on GPIOs
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; GPIOR0 - bit 0: Whether we need to refresh the display
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; GPIOR0 - bit 1: Set when INT_INT0 has received a new bit
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; GPIOR0 - bit 2: The value of the new bit received
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; GPIOR0 - bit 4: input mode enabled
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; Notes on register usage
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; R0 - R3: 4 low bits are for digit, 5th bit is for dot. other bits are unused.
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;
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; Notes on AFF1-4
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; They are reversed (depending on how you see things...). They read right to
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; left. That means that AFF1 is least significant, AFF4 is most.
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;
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; Input mode counter
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; When in input mode, TIMER0_OVF, instead of setting the refresh flag, increases
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; the counter. When it reaches 3, we timeout and consider input invalid.
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;
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; Input procedure
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;
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; Input starts at INT_INT0. What it does there is very simple: is sets up a flag
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; telling it received something and conditionally sets another flag with the
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; value of the received bit.
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;
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; While we do that, we have the input loop eagerly checking for that flag. When
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; it triggers, it records the bit in R18. The way it does so is that it inits
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; R18 at 1 (not 0), then for every bit, it left shifts R18, then adds the new
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; bit. When the 6th bit of R18 is set, it means we have every bit we need, we
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; can flush it into Z.
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; Z points directly to R3, then R2, then R1, then R0. Because display refresh
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; is disabled during input, it won't result in weird displays, and because
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; partial numbers result in error display, then partial result won't lead to
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; weird displays, just error displays.
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;
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; When input mode begins, we change Z to point to R3 (the first digit we
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; receive) and we decrease the Z pointer after every digit we receive. When we
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; receive the last bit of the last digit and that we see that R30 is 0, we know
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; that the next (and last) digit is the checksum.
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.inc "avr.h"
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.inc "tn254585.h"
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.inc "tn45.h"
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; pins
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.equ RCLK 0 ; on PORTB
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.equ SRCLK 3 ; on PORTB
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.equ SER_DP 4 ; on PORTB
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.equ INSER 1 ; on PORTB
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; Let's begin!
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.org 0x0000
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RJMP MAIN
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RJMP INT_INT0
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RETI ; PCINT0
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RETI ; TIMER1_COMPA
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RETI ; TIMER1_OVF
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RJMP INT_TIMER0_OVF
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MAIN:
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LDI R16, RAMEND&0xff
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OUT SPL, R16
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LDI R16, RAMEND}8
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OUT SPH, R16
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SBI DDRB, RCLK
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SBI DDRB, SRCLK
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SBI DDRB, SER_DP
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; we generally keep SER_DP high to avoid lighting DP
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SBI PORTB, SER_DP
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; target delay: 600us. At 1Mhz, that's 75 ticks with a 1/8 prescaler.
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LDI R16, 0x02 ; CS01, 1/8 prescaler
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OUT TCCR0B, R16
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LDI R16, 0xb5 ; TOP - 75 ticks
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OUT TCNT0, R16
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; Enable TIMER0_OVF
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IN R16, TIMSK
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ORI R16, 0x02 ; TOIE0
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OUT TIMSK, R16
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; Generate interrupt on rising edge of INT0
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IN R16, MCUCR
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ORI R16, 0b00000011 ; ISC00 + ISC01
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OUT MCUCR, R16
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IN R16, GIMSK
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ORI R16, 0b01000000 ; INT0
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OUT GIMSK, R16
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; we never use indirect addresses above 0xff through Z and never use
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; R31 in other situations. We can set it once and forget about it.
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CLR R31 ; high Z
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; put 4321 in R2-5
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CLR R30 ; low Z
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LDI R16, 0x04
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ST Z+, R16 ; 4
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DEC R16
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ST Z+, R16 ; 3
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DEC R16
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ST Z+, R16 ; 2
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DEC R16
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ORI R16, 0b00010000 ; DP
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ST Z, R16 ; 1
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CLR R30 ; replace Z to 0
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SEI
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LOOP:
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RCALL INPT_CHK ; verify that we shouldn't enter input mode
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SBIC GPIOR0, 0 ; refesh flag cleared? skip next
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RCALL RDISP
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RJMP LOOP
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; ***** DISPLAY *****
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; refresh display with current number
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RDISP:
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; First things first: setup the timer for the next time
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LDI R16, 0xb5 ; TOP - 75 ticks
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OUT TCNT0, R16
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CBI GPIOR0, 0 ; Also, clear the refresh flag
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; Let's begin with the display selector. We select one display at once
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; (not ready for multi-display refresh operations yet). Let's decode our
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; binary value from R30 into R16.
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MOV R6, R30
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INC R6 ; we need values 1-4, not 0-3
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LDI R16, 0x01
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RDISP1:
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DEC R6
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BREQ RDISP2 ; == 0? we're finished
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LSL R16
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RJMP RDISP1
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; select a digit to display
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; we do so in a clever way: our registers just happen to be in SRAM
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; locations 0x00, 0x01, 0x02 and 0x03. Handy eh!
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RDISP2:
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LD R18, Z+ ; Indirect load of Z into R18 then increment
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CPI R30, 4
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BRCS RDISP3 ; lower than 4 ? don't reset
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CLR R30 ; not lower than 4? reset
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; in the next step, we're going to join R18 and R16 together, but
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; before we do, we have one thing to process: R18's 5th bit. If it's
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; high, it means that DP is highlighted. We have to store this
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; information in R6 and use it later. Also, we have to clear the higher
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; bits of R18.
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RDISP3:
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SBRC R18, 4 ; 5th bit cleared? skip next
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INC R6 ; if set, then set R6 as well
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ANDI R18, 0xf ; clear higher bits
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; Now we have our display selector in R16 and our digit to display in
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; R18. We want it all in R18.
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SWAP R18 ; digit goes in high "nibble"
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OR R18, R16
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; While we send value to the shift register, SER_DP will change.
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; Because we want to avoid falsely lighting DP, we need to disable
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; output (disable OE) while that happens. This is why we set RCLK,
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; which is wired to OE too, HIGH (OE disabled) at the beginning of
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; the SR operation.
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;
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; Because RCLK was low before, this triggers a "buffer clock" on
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; the SR, but it doesn't matter because the value that was there
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; before has just been invalidated.
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SBI PORTB, RCLK ; high
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RCALL SENDSR
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; Flush out the buffer with RCLK
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CBI PORTB, RCLK ; OE enabled, but SR buffer isn't flushed
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NOP
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SBI PORTB, RCLK ; SR buffer flushed, OE disabled
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NOP
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CBI PORTB, RCLK ; OE enabled
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; We're finished! Oh no wait, one last thing: should we highlight DP?
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; If we should, then we should keep SER_DP low rather than high for this
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; SR round.
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SBI PORTB, SER_DP ; SER_DP generally kept high
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SBRC R6, 0 ; R6 is cleared? skip DP set
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CBI PORTB, SER_DP ; SER_DP low highlight DP
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RET ; finished for real this time!
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; send R18 to shift register.
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; We send highest bits first so that QH is the MSB and QA is the LSB
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; low bits (QD - QA) control display's power
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; high bits (QH - QE) select the glyph
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SENDSR:
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LDI R16, 8 ; we will loop 8 times
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CBI PORTB, SER_DP ; low
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SBRC R18, 7 ; if latest bit isn't cleared, set SER_DP high
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SBI PORTB, SER_DP ; high
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RCALL TOGCP
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LSL R18 ; shift our data left
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DEC R16
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BRNE SENDSR+2 ; not zero yet? loop! (+2 to avoid reset)
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RET
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; toggle SRCLK, waiting 1us between pin changes
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TOGCP:
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CBI PORTB, SRCLK ; low
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NOP ; At 1Mhz, this is enough for 1us
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SBI PORTB, SRCLK ; high
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RET
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; ***** INPUT MODE *****
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; check whether we should enter input mode and enter it if needed
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INPT_CHK:
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SBIS GPIOR0, 1 ; did we just trigger INT_INT0?
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RET ; no? return
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; yes? continue in input mode
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; Initialize input mode and start the loop
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INPT_BEGIN:
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SBI GPIOR0, 4 ; enable input mode
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CBI GPIOR0, 1 ; The first trigger was an empty one
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; At 1/8 prescaler, a "full" counter overflow is 2048us. That sounds
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; about right for an input timeout. So we co the easy route and simply
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; clear TCNT0 whenever we want to reset the timer
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OUT TCNT0, R5 ; R5 == 0
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CBI GPIOR0, 0 ; clear refresh flag in case it was just set
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LDI R30, 0x04 ; make Z point on R3+1 (we use pre-decrement)
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LDI R18, 0x01 ; initialize input buffer
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; loop in input mode. When in input mode, we don't refresh the display, we use
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; all our processing power to process input.
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INPT_LOOP:
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RCALL INPT_READ
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; Check whether we've reached timeout
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SBIC GPIOR0, 0 ; refesh flag cleared? skip next
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RCALL INPT_TIMEOUT
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SBIC GPIOR0, 4 ; input mode cleared? skip next, to INPT_END
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RJMP INPT_LOOP ; not cleared? loop
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INPT_END:
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; We received all our date or reached timeout. let's go back in normal
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; mode.
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CLR R30 ; Ensure Z isn't out of bounds
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SBI GPIOR0, 0 ; set refresh flag so we start refreshing now
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RET
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; Read, if needed, the last received bit
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INPT_READ:
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SBIS GPIOR0, 1
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RET ; flag cleared? nothing to do
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; Flag is set, we have to read
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CBI GPIOR0, 1 ; unset flag
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LSL R18
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SBIC GPIOR0, 2 ; data flag cleared? skip next
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INC R18
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; Now, let's check if we have our 5 digits
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SBRC R18, 5 ; 6th bit cleared? nothing to do
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RCALL INPT_PUSH
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OUT TCNT0, R5 ; clear timeout counter
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RET
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; Push the digit currently in R18 in Z and reset R18.
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INPT_PUSH:
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ANDI R18, 0b00011111 ; Remove 6th bit flag
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TST R30 ; is R30 zero?
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BREQ INPT_CHECKSUM ; yes? it means we're at checksum phase.
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; Otherwise, its a regular digit push
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ST -Z, R18
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LDI R18, 0x01
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RET
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INPT_CHECKSUM:
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CBI GPIOR0, 4 ; clear input mode, whether we error or not
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MOV R16, R0
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ADD R16, R1
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ADD R16, R2
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ADD R16, R3
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; only consider the first 5 bits of the checksum since we can't receive
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; more. Otherwise, we couldn't possibly validate a value like 9999
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ANDI R16, 0b00011111
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CP R16, R18
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BRNE INPT_ERROR
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RET
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INPT_TIMEOUT:
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CBI GPIOR0, 4 ; timeout reached, clear input flag
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; continue to INPT_ERROR
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INPT_ERROR:
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LDI R16, 0x0c ; some weird digit
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MOV R0, R16
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MOV R1, R16
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MOV R2, R16
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MOV R3, R16
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RET
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; ***** INTERRUPTS *****
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; Record received bit
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; The main loop has to be fast enough to process that bit before we receive the
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; next one!
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; no SREG fiddling because no SREG-modifying instruction
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INT_INT0:
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CBI GPIOR0, 2 ; clear received data
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SBIC PINB, INSER ; INSER clear? skip next
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SBI GPIOR0, 2 ; INSER set? record this
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SBI GPIOR0, 1 ; indicate that we've received a bit
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RETI
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; Set refresh flag whenever timer0 overflows
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; no SREG fiddling because no SREG-modifying instruction
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INT_TIMER0_OVF:
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SBI GPIOR0, 0
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RETI
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