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aa8df95f7d
Also, add a "real world" example in AVRA tests, a blink program on a ATtiny45. Some instructions are commented out because they aren't implemented yet, but not many. The output of the program has been verified against AVRA's own output.
135 lines
1.8 KiB
Plaintext
135 lines
1.8 KiB
Plaintext
The AVR instruction set is a bit more regular than z80's, which allows us for
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simpler upcode spitting logic (simplicity which is lost when we need to take
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into account all AVR models and instruction constraints on each models). This
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file categorizes all available ops with their opcode signature. X means upcode
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bit.
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Categories are in descending order of "popularity"
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Mnemonics with "*" are a bit special.
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### 16-bit
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## Plain
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XXXX XXXX XXXX XXXX
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BREAK, CLC, CLH, CLI, CLN, CLS, CLT, CLV, CLZ, EICALL, EIJMP, ELPM*, ICALL,
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IJMP, NOP, RET, RETI, SEC, SEH, SEI, SEN, SES, SET, SEV, SEZ, SLEEP, SPM*, WDR
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## Rd(5)
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XXXX XXXd dddd XXXX
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ASR, COM, DEC, ELPM*, INC, LAC, LAS, LAT, LD*, LPM*, LSR, NEG, POP, PUSH, ROR,
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ST*, SWAP, XCH
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## Rd(5) + Rr(5)
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XXXX XXrd dddd rrrr
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ADC, ADD, AND, CLR, CP, CPC, CPSE, EOR, MOV, MUL, OR, ROL*, SBC, SUB,
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TST*
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## k(7)
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XXXX XXkk kkkk kXXX
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BRCC, BRCS, BREQ, BRGE, BRHC, BRHS, BRID, BRIE, BRLO, BRLT, BRMI, BRNE, BRPL,
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BRSH, BRTC, BRTS, BRVC, BRVS
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## Rd(4) + K(8)
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XXXX KKKK dddd KKKK
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ANDI, CBR*, CPI, LDI, ORI, SBCI, SBR, SUBI
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## Rd(5) + bit
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XXXX XXXd dddd Xbbb
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BLD, BST, SBRC, SBRS
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## A(5) + bit
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XXXX XXXX AAAA Abbb
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CBI, SBI, SBIC, SBIS
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## Rd(3) + Rr(3)
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XXXX XXXX Xddd Xrrr
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FMUL, FMULS, FMULSU, MULSU
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## Rd(4) + Rr(4)
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XXXX XXXX dddd rrrr
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MOVW, MULS
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## Rd(5) + A(6)
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XXXX XAAd dddd AAAA
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IN, OUT
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## Rd(4) + k(7)
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XXXX Xkkk dddd kkkk
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LDS*, STS*
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## Rd(2) + K
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XXXX XXXX KKdd KKKK
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ADIW, SBIW
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## Rd(4)
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XXXX XXXX dddd XXXX
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SER
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## K(4)
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XXXX XXXX KKKK XXXX
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DES
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## k(12)
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XXXX kkkk kkkk kkkk
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RCALL, RJMP
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## SREG
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XXXX XXXX Xsss XXXX
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BCLR, BSET
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## SREG + k(7)
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XXXX XXkk kkkk ksss
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BRBC, BRBS
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### 32-bit
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## k(22)
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XXXX XXXk kkkk XXXk
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kkkk kkkk kkkk kkkk
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CALL, JMP
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## Rd(5) + k(16)
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XXXX XXXd dddd XXXX
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kkkk kkkk kkkk kkkk
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LDS*, STS*
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