( Save ACIA conf )
ACIA_CTL
: ACIA_CTL [ LITN ] ;
ACIA_IO
: ACIA_IO [ LITN ] ;
ACIA_MEM
: ACIA_MEM [ LITN ] ;
( Memory layout
  +0 ACIAR>
  +2 ACIAW>
  +4 ACIA(
  +6 ACIA)
)

(xentry) ~ACIA
    AF PUSHqq,
    HL PUSHqq,
    DE PUSHqq,

	( Read our character from ACIA into our BUFIDX )
    ACIA_CTL INAn,
    0x01 ANDn,   ( is ACIA rcv buf full? )
    JRZ, L2 FWR ( end, no, wrong interrupt cause. )

    ( +2 == ACIAW> )
    ACIA_MEM 2 + LDHL(nn),
    ( is it == to ACIAR>? )
    ( +0 == ACIAR> )
    DE ACIA_MEM LDdd(nn),
    ( carry cleared from ANDn above )
    DE SBCHLss,
    JRZ, L3 FWR ( end, buffer full )

    DE ADDHLss, ( restore ACIAW> )
    ( buffer not full, let's write )
    ACIA_IO INAn,
    (HL) A LDrr,

    ( advance W> )
    HL INCss,
    ( +2 == ACIAW> )
    ACIA_MEM 2 + LD(nn)HL,
    ( +6 == ACIA) )
    DE ACIA_MEM 6 + LDdd(nn),
    DE SUBHLss,
    JRNZ, L4 FWR ( skip )
    ( end of buffer reached )
    ( +4 == ACIA( )
    ACIA_MEM 4 + LDHL(nn),
    ( +2 == ACIAW> )
    ACIA_MEM 2 + LD(nn)HL,
L4 FSET ( skip )
L3 FSET L2 FSET ( end )

    DE POPqq,
    HL POPqq,
    AF POPqq,
    EI,
    RETI,