mirror of https://github.com/hsoft/collapseos.git
rc2014: separate SPI relay and SDC drivers
My intention is to reuse the SPI relay to program AVR MCUs from a RC2014.
This commit is contained in:
Virgil Dupras
parent
1ac7038863
commit
f09aa0603c
3
blk/580
3
blk/580
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@ -4,4 +4,5 @@ Support code for the RC2014 recipe. Contains drivers for the
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ACIA, SD card and AT28 EEPROM.
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581 ACIA 590 AT28 EEPROM
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600 SD card 618 Xcomp unit
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595 SPI relay 600 SD card
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618 Xcomp unit
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@ -0,0 +1,12 @@
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SPI relay driver
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This driver is designed for a ad-hoc adapter card that acts as a
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SPI relay between the z80 bus and the SPI device. Sending any-
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thing on SPI_CSLOW and SPI_CSHIGH is expected to select/deselect
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the device, and writing to SPI_DATA is expected to initiate a
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byte exchange. The result of the exchange is excpected to be re-
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trieved by reading SPI_DATA.
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Provides (spie) (enable), (spid) (disable), (spix) (xchange).
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Load driver with "596 LOAD".
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@ -0,0 +1,12 @@
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CODE (spix) ( n -- n )
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HL POP,
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chkPS,
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A L LDrr,
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SPI_DATA OUTiA,
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NOP, NOP, ( let SPI relay breathe )
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SPI_DATA INAi,
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L A LDrr,
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HL PUSH,
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;CODE
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CODE (spie) SPI_CSLOW OUTiA, ;CODE
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CODE (spid) SPI_CSHIGH OUTiA, ;CODE
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12
blk/600
12
blk/600
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@ -1,13 +1,11 @@
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SD Card driver
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Load range: 602-616
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Load range: 603-616
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This driver is designed for a ad-hoc adapter card that acts as a
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SPI relay between the z80 bus and the SD card. That adapter is
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expected to pull CS low when something is written to SDC_CSLOW,
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high on SDC_CSHIGH and to initiate a SPI exchange when a byte is
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written to SDC_SPI, the result of that exchange being fetched
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with a read to SDC_SPI.
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SPI relay between the z80 bus and the SD card. It requires a SPI
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driver providing (spix), (spie) and (spid), which oh surprise!
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is included in Collapse OS at B595.
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Through that layer, this driver implements the SDC protocol
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Through that layer, this driver implements the SDC protocol
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allowing it to provide BLK@ and BLK!.
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12
blk/602
12
blk/602
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@ -1,12 +0,0 @@
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( Initiate SPI exchange with the SD card. n is the data to
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send. )
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CODE _sdcSR ( n -- n )
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HL POP,
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chkPS,
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A L LDrr,
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SDC_SPI OUTiA,
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NOP, NOP,
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SDC_SPI INAi,
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L A LDrr,
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HL PUSH,
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;CODE
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2
blk/603
2
blk/603
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@ -1,5 +1,3 @@
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CODE _sdcSel SDC_CSLOW OUTiA, ;CODE
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CODE _sdcDesel SDC_CSHIGH OUTiA, ;CODE
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( Computes n into crc c with polynomial 0x1021 )
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CODE _crc16 ( c n -- c )
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HL POP, ( n ) DE POP, ( c )
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4
blk/604
4
blk/604
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@ -1,8 +1,8 @@
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( -- n )
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: _idle 0xff _sdcSR ;
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: _idle 0xff (spix) ;
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( -- n )
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( _sdcSR 0xff until the response is something else than 0xff
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( spix 0xff until the response is something else than 0xff
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for a maximum of 20 times. Returns 0xff if no response. )
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: _wait
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0 ( cnt )
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2
blk/607
2
blk/607
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@ -1,3 +1,3 @@
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( send-and-crc7 )
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( n c -- c )
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: _s+crc SWAP DUP _sdcSR DROP _crc7 ;
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: _s+crc SWAP DUP (spix) DROP _crc7 ;
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2
blk/608
2
blk/608
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@ -11,6 +11,6 @@
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SWAP 256 /MOD ROT ( h l crc )
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_s+crc _s+crc ( crc )
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0x01 OR ( ensure stop bit )
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_sdcSR DROP ( send CRC )
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(spix) DROP ( send CRC )
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_wait ( wait for a valid response... )
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;
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6
blk/609
6
blk/609
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@ -1,15 +1,15 @@
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( cmd arg1 arg2 -- r )
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( Send a command that expects a R1 response, handling CS. )
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: SDCMDR1 _sdcSel _cmd _sdcDesel ;
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: SDCMDR1 (spie) _cmd (spid) ;
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( cmd arg1 arg2 -- r arg1 arg2 )
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( Send a command that expects a R7 response, handling CS. A R7
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is a R1 followed by 4 bytes. arg1 contains bytes 0:1, arg2
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has 2:3 )
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: SDCMDR7
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_sdcSel
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(spie)
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_cmd ( r )
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_idle 8 LSHIFT _idle + ( r arg1 )
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_idle 8 LSHIFT _idle + ( r arg1 arg2 )
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_sdcDesel
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(spid)
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;
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2
blk/610
2
blk/610
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@ -1,4 +1,4 @@
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: _err _sdcDesel ABORT" SDerr" ;
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: _err (spid) ABORT" SDerr" ;
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( Tight definition ahead, pre-comment.
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4
blk/612
4
blk/612
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@ -1,5 +1,5 @@
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: _sdc@ ( dstaddr blkno -- )
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_sdcSel 0x51 ( CMD17 ) 0 ROT ( a cmd 0 blkno ) _cmd
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(spie) 0x51 ( CMD17 ) 0 ROT ( a cmd 0 blkno ) _cmd
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IF _err THEN
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_wait 0xfe = NOT IF _err THEN
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0 SWAP ( crc a )
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@ -11,5 +11,5 @@
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LOOP
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DROP ( crc1 )
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_idle 8 LSHIFT _idle + ( crc2 )
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_wait DROP _sdcDesel
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_wait DROP (spid)
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= NOT IF _err THEN ;
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10
blk/614
10
blk/614
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@ -1,16 +1,16 @@
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: _sdc! ( srcaddr blkno -- )
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_sdcSel 0x58 ( CMD24 ) 0 ROT ( a cmd 0 blkno ) _cmd
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(spie) 0x58 ( CMD24 ) 0 ROT ( a cmd 0 blkno ) _cmd
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IF _err THEN
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_idle DROP 0xfe _sdcSR DROP
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_idle DROP 0xfe (spix) DROP
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0 SWAP ( crc a )
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512 0 DO ( crc a )
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C@+ ( crc a+1 n )
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ROT OVER ( a n crc n )
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_crc16 ( a n crc )
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SWAP ( a crc n )
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_sdcSR DROP ( a crc )
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(spix) DROP ( a crc )
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SWAP ( crc a )
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LOOP
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DROP ( crc ) 256 /MOD ( lsb msb )
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_sdcSR DROP _sdcSR DROP
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_wait DROP _sdcDesel ;
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(spix) DROP (spix) DROP
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_wait DROP (spid) ;
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2
blk/618
2
blk/618
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@ -1,8 +1,6 @@
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0xff00 CONSTANT RS_ADDR 0xfffa CONSTANT PS_ADDR
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RS_ADDR 0x80 - CONSTANT SYSVARS
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0x8000 CONSTANT HERESTART
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4 CONSTANT SDC_SPI
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5 CONSTANT SDC_CSLOW 6 CONSTANT SDC_CSHIGH
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582 LOAD ( acia decl )
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212 LOAD ( z80 assembler )
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262 LOAD ( xcomp ) 282 LOAD ( boot.z80.decl )
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@ -71,11 +71,17 @@ instead.
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## Building your binary
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The binary built in the base recipe doesn't have SDC drivers. Using the same
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instructions as in the `eeprom` recipe, you'll need to insert those drivers.
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instructions as in the `eeprom` recipe, you'll need to assemble a binary with
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those drivers. First, we need drivers for the SPI relay. This is done by
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declaring `SPI_DATA`, `SPI_CSLOW` and `SPI_CSHIGH`, which are respectively `4`,
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`5` and `6` in our relay design. You can then load the driver with `596 LOAD`.
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This driver provides `(spix)`, `(spie)` and `(spid)` which are then used in the
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SDC driver.
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The SDC driver is at B600. It gives you a load range. This means that what
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you need to insert in `xcomp` will look like:
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602 616 LOADR ( sdc )
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603 616 LOADR ( sdc )
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You also need to add `BLK$` to the init sequence.
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@ -104,7 +110,7 @@ If there is no error message, we're fine. Then, we need to hook `BLK@*` and
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And thats it! You have full access to disk block mechanism:
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102 LOAD
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105 LOAD
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BROWSE
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(at this moment, the driver is a bit slow though...)
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