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Add layer of indirection to EMIT

This would allow things like temporary giving control to the *CL
line on the TRS-80. For example... A very far fetched example. Not
at all the only *raison d'etre* of the layer...
This commit is contained in:
Virgil Dupras 2020-05-01 20:05:15 -04:00
parent 5bf3baff05
commit ecca70c7f3
17 changed files with 77 additions and 73 deletions

18
blk/081
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@ -1,16 +1,16 @@
(cont.)
RAMSTART INITIAL_SP +53 readln's variables
+02 CURRENT +55 adev's variables
+04 HERE +57 blk's variables
+06 C<?* +59 z80a's variables
+08 C<* override +5b FUTURE USES
+0a PARSEPTR +70 DRIVERS
+0c C<* +80 RAMEND
+0e WORDBUF
RAMSTART INITIAL_SP +55 EMITPTR override
+02 CURRENT +57 readln's variables
+04 HERE +59 blk's variables
+06 C<? +5b z80a's variables
+08 C<* override +5d adev's variables
+0a PARSEPTR +5f FUTURE USES
+0c C<* +70 DRIVERS
+0e WORDBUF +80 RAMEND
+2e BOOT C< PTR
+4e INTJUMP
+51 CURRENTPTR
+53 EMITPTR
(cont.)

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@ -1,9 +1,9 @@
: ADEVMEM+ 0x55 RAM+ @ + ;
: ADEVMEM+ 0x5d RAM+ @ + ;
: A@* 0 ADEVMEM+ ;
: A!* 2 ADEVMEM+ ;
: ADEV$
H@ 0x55 RAM+ !
H@ 0x5d RAM+ !
4 ALLOT
['] C@ A@* !
['] C! A!* !

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@ -1,9 +1,9 @@
: Z80AMEM+ 0x59 RAM+ @ + ;
: Z80AMEM+ 0x5b RAM+ @ + ;
: ORG 0 Z80AMEM+ ;
: BIN( 2 Z80AMEM+ ;
: L1 4 Z80AMEM+ ; : L2 6 Z80AMEM+ ;
: L3 8 Z80AMEM+ ; : L4 10 Z80AMEM+ ;
: Z80A$ H@ 0x59 RAM+ ! 12 ALLOT 0 BIN( ! ;
: Z80A$ H@ 0x5b RAM+ ! 12 ALLOT 0 BIN( ! ;
: A 7 ; : B 0 ; : C 1 ; : D 2 ;
: E 3 ; : H 4 ; : L 5 ; : (HL) 6 ;
: BC 0 ; : DE 1 ; : HL 2 ; : AF 3 ; : SP AF ;

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@ -11,5 +11,5 @@ ACIA_MEM
+4 ACIA(
+6 ACIA) )
353 356 LOADR
353 355 LOADR

17
blk/355 Normal file
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@ -0,0 +1,17 @@
IFZ, ( end of buffer reached? )
( yes )
( +4 == ACIA( )
ACIA_MEM 4 + LDHL(nn),
( +2 == ACIAW> )
ACIA_MEM 2+ LD(nn)HL,
THEN,
THEN,
THEN,
DE POPqq,
HL POPqq,
AF POPqq,
EI,
RETI,

16
blk/356
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@ -1,16 +0,0 @@
IFZ, ( end of buffer reached? )
( yes )
( +4 == ACIA( )
ACIA_MEM 4 + LDHL(nn),
( +2 == ACIAW> )
ACIA_MEM 2+ LD(nn)HL,
THEN,
THEN,
THEN,
DE POPqq,
HL POPqq,
AF POPqq,
EI,
RETI,

30
blk/359
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@ -1,16 +1,16 @@
: ACIA$
H@ DUP DUP ACIA( ! ACIAR> !
1+ ACIAW> ! ( write index starts one position later )
ACIABUFSZ ALLOT
H@ ACIA) !
( setup ACIA
CR7 (1) - Receive Interrupt enabled
CR6:5 (00) - RTS low, transmit interrupt disabled.
CR4:2 (101) - 8 bits + 1 stop bit
CR1:0 (10) - Counter divide: 64 )
0b10010110 ACIA_CTL PC!
( setup interrupt )
0xc3 0x4e RAM+ C! ( c3==JP, 4e==INTJUMP )
['] ~ACIA 0x4f RAM+ !
(im1)
: KEY
( inc then fetch )
ACIAR> @ 1+ DUP ACIA) @ = IF
DROP ACIA( @
THEN
( As long as R> == W>-1, it means that buffer is empty )
BEGIN DUP ACIAW> @ = NOT UNTIL
ACIAR> !
ACIAR> @ C@
;
: (emit)
( As long at CTL bit 1 is low, we are transmitting. wait )
BEGIN ACIA_CTL PC@ 0x02 AND UNTIL
( The way is clear, go! )
ACIA_IO PC!
;

33
blk/360
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@ -1,16 +1,17 @@
: KEY
( inc then fetch )
ACIAR> @ 1+ DUP ACIA) @ = IF
DROP ACIA( @
THEN
( As long as R> == W>-1, it means that buffer is empty )
BEGIN DUP ACIAW> @ = NOT UNTIL
ACIAR> !
ACIAR> @ C@
;
: EMIT
( As long at CTL bit 1 is low, we are transmitting. wait )
BEGIN ACIA_CTL PC@ 0x02 AND UNTIL
( The way is clear, go! )
ACIA_IO PC!
;
: ACIA$
H@ DUP DUP ACIA( ! ACIAR> !
1+ ACIAW> ! ( write index starts one position later )
ACIABUFSZ ALLOT
H@ ACIA) !
( setup ACIA
CR7 (1) - Receive Interrupt enabled
CR6:5 (00) - RTS low, transmit interrupt disabled.
CR4:2 (101) - 8 bits + 1 stop bit
CR1:0 (10) - Counter divide: 64 )
0b10010110 ACIA_CTL PC!
( setup interrupt )
0xc3 0x4e RAM+ C! ( c3==JP, 4e==INTJUMP )
['] ~ACIA 0x4f RAM+ !
['] (emit) 0x53 RAM+ ! ( 53==EMITPTR )
(im1) ;

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@ -1,15 +1,15 @@
: BOOT
0x02 RAM+ CURRENT* !
LIT< (parse) (find) DROP (parse*) !
( 2e == SYSTEM SCRATCHPAD )
CURRENT @ 0x2e RAM+ !
CURRENT @ 0x2e RAM+ ! ( 2e == BOOT C< PTR)
0 0x08 RAM+ ! ( 08 == C<* override )
LIT< (emit) (find) DROP 0x53 RAM+ ! ( 53 == EMITPTR )
0 0x55 RAM+ ! ( 55 == EMITPTR override )
( 0c == C<* )
LIT< (boot<) (find) DROP 0x0c RAM+ !
( boot< always has a char waiting. 06 == C<?* )
1 0x06 RAM+ !
LIT< INIT (find)
IF EXECUTE
ELSE DROP INTERPRET THEN
IF EXECUTE ELSE DROP INTERPRET THEN
;

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@ -1,4 +1,6 @@
( EMIT is needed for this unit to compile )
: EMIT
( 0x53==EMITPTR 0x55==override )
85 RAM+ @ DUP NOT IF DROP 83 RAM+ @ THEN EXECUTE ;
: (print)
BEGIN

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@ -1,5 +1,5 @@
64 CONSTANT INBUFSZ
: RDLNMEM+ 0x53 RAM+ @ + ;
: RDLNMEM+ 0x57 RAM+ @ + ;
( current position in INBUF )
: IN> 0 RDLNMEM+ ;
( points to INBUF )

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@ -1,7 +1,7 @@
( Initializes the readln subsystem )
: RDLN$
( 53 == rdln's memory )
H@ 0x53 RAM+ !
( 57 == rdln's memory )
H@ 0x57 RAM+ !
( 2 for IN>, plus 2 for extra bytes after buffer: 1 for
the last typed 0x0a and one for the following NULL. )
INBUFSZ 4 + ALLOT

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@ -1,4 +1,4 @@
: BLKMEM+ 0x57 RAM+ @ + ;
: BLKMEM+ 0x59 RAM+ @ + ;
( n -- Fetches block n and write it to BLK( )
: BLK@* 0 BLKMEM+ ;
( n -- Write back BLK( to storage at block n )

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@ -1,5 +1,5 @@
: BLK$
H@ 0x57 RAM+ !
H@ 0x59 RAM+ !
( 1024 for the block, 8 for variables )
1032 ALLOT
( LOAD detects end of block with ASCII EOT. This is why

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@ -4,7 +4,7 @@ CODE KEY
L A LDrr, H 0 LDrn,
HL PUSHqq,
;CODE
CODE EMIT
CODE (emit)
BC POPqq, ( c == @DSP arg )
chkPS,
A 0x02 LDrn, ( @DSP )

Binary file not shown.

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@ -16,7 +16,7 @@ H@ 256 /MOD 2 PC! 2 PC!
( Update LATEST )
PC ORG @ 8 + !
," CURRENT @ HERE ! "
," : EMIT 0 PC! ; "
," : (emit) 0 PC! ; CURRENT @ 83 RAM+ ! "
," : KEY 0 PC@ ; "
422 470 XPACKR
," ' KEY 12 RAM+ ! "