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drv/acia: latest bells and whistles
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@ -29,7 +29,7 @@ ACIA_MEM: Address in memory that can be used variables shared
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: ACIA$
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H@ DUP DUP ACIA( ! ACIAR> !
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1 + ACIAW> ! ( write index starts one position later )
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1+ ACIAW> ! ( write index starts one position later )
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ACIABUFSZ ALLOT
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H@ ACIA) !
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( setup ACIA
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@ -49,7 +49,7 @@ ACIA_MEM: Address in memory that can be used variables shared
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: KEY
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( inc then fetch )
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ACIAR> @ 1 + DUP ACIA) @ = IF
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ACIAR> @ 1+ DUP ACIA) @ = IF
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DROP ACIA( @
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THEN
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61
drv/acia.z80
61
drv/acia.z80
@ -20,37 +20,38 @@ ACIA_MEM
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( Read our character from ACIA into our BUFIDX )
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ACIA_CTL INAn,
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0x01 ANDn, ( is ACIA rcv buf full? )
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JRZ, L2 FWR ( end, no, wrong interrupt cause. )
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IFNZ,
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( correct interrupt cause )
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( +2 == ACIAW> )
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ACIA_MEM 2+ LDHL(nn),
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( is it == to ACIAR>? )
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( +0 == ACIAR> )
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DE ACIA_MEM LDdd(nn),
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( carry cleared from ANDn above )
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DE SBCHLss,
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IFNZ, ( buffer full? )
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( no, continue )
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DE ADDHLss, ( restore ACIAW> )
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( buffer not full, let's write )
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ACIA_IO INAn,
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(HL) A LDrr,
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( +2 == ACIAW> )
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ACIA_MEM 2 + LDHL(nn),
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( is it == to ACIAR>? )
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( +0 == ACIAR> )
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DE ACIA_MEM LDdd(nn),
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( carry cleared from ANDn above )
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DE SBCHLss,
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JRZ, L3 FWR ( end, buffer full )
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DE ADDHLss, ( restore ACIAW> )
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( buffer not full, let's write )
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ACIA_IO INAn,
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(HL) A LDrr,
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( advance W> )
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HL INCss,
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( +2 == ACIAW> )
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ACIA_MEM 2 + LD(nn)HL,
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( +6 == ACIA) )
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DE ACIA_MEM 6 + LDdd(nn),
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DE SUBHLss,
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JRNZ, L4 FWR ( skip )
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( end of buffer reached )
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( +4 == ACIA( )
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ACIA_MEM 4 + LDHL(nn),
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( +2 == ACIAW> )
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ACIA_MEM 2 + LD(nn)HL,
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L4 FSET ( skip )
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L3 FSET L2 FSET ( end )
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( advance W> )
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HL INCss,
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( +2 == ACIAW> )
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ACIA_MEM 2+ LD(nn)HL,
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( +6 == ACIA) )
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DE ACIA_MEM 6 + LDdd(nn),
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DE SUBHLss,
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IFZ, ( end of buffer reached? )
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( yes )
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( +4 == ACIA( )
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ACIA_MEM 4 + LDHL(nn),
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( +2 == ACIAW> )
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ACIA_MEM 2+ LD(nn)HL,
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THEN,
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THEN,
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THEN,
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DE POPqq,
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HL POPqq,
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