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recipes/rc2014/sdcard: make spi relay design multi-devices
Also, fix the SPI relay driver to properly AND-away the result of the CTL read. Tested with a real prototype, works fine.
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@ -2,7 +2,7 @@ CODE (spix) ( n -- n )
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HL POP, chkPS, A L LDrr,
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SPI_DATA OUTiA,
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( wait until xchg is done )
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BEGIN, SPI_CTL INAi, A ORr, JRNZ, AGAIN,
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BEGIN, SPI_CTL INAi, 1 ANDi, JRNZ, AGAIN,
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SPI_DATA INAi,
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L A LDrr,
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HL PUSH,
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@ -1,12 +1,5 @@
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# Accessing a MicroSD card
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Warning: this recipe is temporarily broken. The schema below hasn't yet been
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updated to work with the new SPI relay protocol. If you've already built an
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old design, use an earlier commit or work around it in the SPI driver it should
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only be a matter of testing the input value for zero-ness to decide whether we
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ping the CSLOW or CSHIGH port. If you haven't, wait a little bit before building
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one: the upcoming design is better.
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SD cards are great because they are accessible directly. No supporting IC is
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necessary. The easiest way to access them is through the SPI protocol.
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@ -25,57 +18,57 @@ subsystem (B420) to drive a SD card.
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* A proto board + header pins with 39 positions so we can make a RC2014 card.
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* Diodes, resistors and stuff
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* 40106 (Inverter gates)
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* 4011 (NAND gates)
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* 74xx139 (Decoder)
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* 74xx138 (Decoder)
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* 74xx375 (Latches)
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* 74xx125 (Buffer)
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* 74xx161 (Binary counter)
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* 74xx165 (Parallel input shift register)
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* 74xx595 (Shift register)
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## Building the SPI relay
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The [schematic][schematic] supplied with this recipe works well with the SD
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Card subsystem (B420). Of course, it's not the only possible design that
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works, but I think it's one of the most straighforwards.
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![SPI relay](spirelay.jpg)
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The basic idea with this relay is to have one shift register used as input,
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loaded in parallel mode from the z80 bus and a shift register that takes the
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serial input from `MISO` and has its output wired to the z80 bus.
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The schematic above works well with the SD Card subsystem (B420). Of course,
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it's not the only possible design that works, but I think it's one of the most
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straighforwards.
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These two shift registers are clocked by a binary counter that clocks exactly
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8 times whenever a write operation on port `4` occurs. Those 8 clocks send
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data we've just received in the `74xx165` into `MOSI` and get `MISO` into the
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`74xx595`.
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This relay communicates through the z80 bus with 2 ports, `DATA` and `CTL` and
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allows up to 4 devices to be connected to it at once, although only one device
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can ever be active at once. This schema only has 2 (and the real prototype I've
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built from it), but the '375 has room for 4. In this schema, `DATA` is port 4,
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`CTL` is port `5`.
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The `74xx139` then takes care of activating the right ICs on the right
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combinations of `IORQ/WR/RD/Axx`.
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We activate a device by sending a bitmask to `CTL`, this will end up in the
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'375 latches and activate the `SS` pin of one of the device, or deactivate them
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all if `0` is sent.
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The rest of the ICs is fluff around this all.
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You then initiate a SPI exchange by sending a byte to send to the `DATA` port.
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This byte will end up in the '165 and the '161 counter will be activated,
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triggering a clock for the SPI exchange. At each clock, a bit is sent to `MOSI`
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from the '161 and received from `MISO` into the '595, which is the byte sent to
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the z80 bus when we read from `DATA`.
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My first idea was to implement the relay with an AVR microcontroller to
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minimize the number of ICs, but it's too slow. We have to be able to respond
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within 300ns! Following that, it became necessary to add a 595 and a 165, but
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if we're going to add that, why not go the extra mile and get rid of the
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microcontroller?
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When the '161 is wired to the system clock, as it is in the schema, two `NOP`s
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are a sufficient delay between your `DATA` write and subsequent `DATA` read.
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To that end, I was heavily inspired by [this design][inspiration].
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However, if you build yourself some kind of clock override and run the '161 at
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something slower than the system clock, those 2 `NOP`s will be too quick. That's
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where that '125 comes into play. When reading `CTL`, it spits `RUNNING` into
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`D0`. This allows you to know when the result of the SPI exchange is ready to be
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fetched. Make sure you `AND` away other bits, because they'll be garbage.
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This board uses port `4` for SPI data, port `5` to pull `CS` low and port `6`
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to pull it high. Port `7` is unused but monopolized by the card.
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The '138 is to determine our current IORQ mode (`DATA`/`CTL` and `WR/RO`), the
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'106 is to provide for those `NOT`s sprinkled around.
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Advice 1: If you make your own design, double check propagation delays!
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Some NAND gates, such as the 4093, are too slow to properly respond within
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a 300ns limit. For example, in my own prototype, I use a 4093 because that's
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what I have in inventory. For the `CS` flip-flop, the propagation delay doesn't
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matter. However, it *does* matter for the `SELECT` line, so I don't follow my
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own schematic with regards to the `M1` and `A2` lines and use two inverters
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instead.
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Please note that this design is inspired by [this design][inspiration].
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Advice 2: Make `SCK` polarity configurable at all 3 endpoints (the 595, the 165
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Advice 1: Make `SCK` polarity configurable at all 3 endpoints (the 595, the 165
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and SPI connector). Those jumpers will be useful when you need to mess with
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polarity in your many tinkering sessions to come.
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Advice 3: Make input `CLK` override-able. SD cards are plenty fast enough for us
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to use the system clock, but you might want to interact with devices that
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Advice 2: Make input `CLK` override-able. SD cards are plenty fast enough for
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us to use the system clock, but you might want to interact with devices that
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require a slower clock.
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## Building your binary
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@ -85,15 +78,14 @@ assemble a binary with those drivers. To do so, you'll modify the xcomp unit
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of the base recipe. Look at `xcomp.fs`, you'll see that we load a block. That's
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our xcomp block (likely, B599). Open it.
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First, we need drivers for the SPI relay. This is done by declaring `SPI_DATA`,
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`SPI_CSLOW` and `SPI_CSHIGH`, which are respectively `4`, `5` and `6` in our
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relay design. We also need to define SPI_DELAY, which we keep to 2 NOPs because
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we use the system clock:
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First, we need drivers for the SPI relay. This is done by declaring `SPI_DATA`
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and `SPI_CTL`, which are respectively `4` and `5` in our relay design.
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: SPI_DELAY NOP, NOP, ;
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You also need to tell the SDC subsystem which SPI device to activate by defining
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the `SDC_DEVID` (1, 2, 4, 8 for device 0, 1, 2 or 3)
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You can then load the driver with `596 LOAD`. This driver provides
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`(spix)`, `(spie)` and `(spid)` which are then used in the SDC driver.
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`(spix)` and `(spie)` which are then used in the SDC driver.
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The SDC driver is at B420. It gives you a load range. This means that what
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you need to insert in `xcomp` will look like:
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@ -139,5 +131,4 @@ Very easy. You see that `/cvm/blkfs` file? You dump it to your raw device.
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For example, if the device you get when you insert your SD card is `/dev/sdb`,
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then you type `cat emul/blkfs | sudo tee /dev/sdb > /dev/null`.
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[schematic]: spirelay.pdf
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[inspiration]: https://www.ecstaticlyrics.com/electronics/SPI/fast_z80_interface.html
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