recipes/rc2014/ps2: add schema

recipes/rc2014/ps2/README.md

@@ -27,12 +27,39 @@ the ACIA.
 
 ## Building the PS/2 interface
 
-TODO. I have yet to draw presentable schematics. By reading `ps2ctl.asm`, you
-might be able to guess how things are wired up.
+Let's start with the PS/2 connector, which has two pins:
 
-It's rather straigtforward: the attiny reads serial data from PS/2 and then
-sends it to the 595. The 595 is wired straight to D7:0 with its `OE` wired to
-address selection + `IORQ` + `RO`
+![PS/2 connector](schema-ps2.png)
+
+Both are connected to the ATtiny45, `CLK` being on `PB2` to have `INT0` on it.
+
+The `DATA` line is multi-use. That is, `PB1` is connected both to the PS/2 data
+line and to the 595's `SER`. This saves us a precious pin.
+
+![ATtiny45](schema-t45.png)
+
+The ATtiny 45 hooks everything together. `CE` comes from the z80 bus, see below.
+
+![74xx595](schema-595.png)
+
+This allows us to supply the z80 bus with data within its 375ns limits. `SRCLR`
+is hooked to the `CE` line so that whenever a byte is read, the 595 is zeroed
+out as fast as possible so that the z80 doesn't read "false doubles".
+
+The 595, to have its `SRCLR` becoming effective, needs a `RCLK` trigger, which
+doesn't happen immediately. It's the ATtiny45, in its `PCINT` interrupt, that
+takes care of doing that trigger (as fast as possible).
+
+![z80](schema-z80.png)
+
+Our device is read only, on one port. That makes the "Chip Enable" (`CE`)
+selection rather simple. In my design, I chose the IO port 8, so I inverted
+`A3`. I chose a 40106 inverter to do that, do as you please for your own design.
+
+I wanted to hook `CE` to a flip flop so that the MCU could relax a bit more
+w.r.t. reacting to its `PB4` pin changes, but I didn't have NAND gates that are
+fast enough in stock, so I went with this design. But otherwise, I would
+probably have gone the flip-flop way. Seems more solid.
 
 ## Using the PS/2 interface