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recipes/rc2014/ps2: add "resend" requests on parity check failures
This commit is contained in:
Virgil Dupras
parent
0f82ebe02d
commit
2c6ab08d51
@ -75,7 +75,7 @@
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; - 2: awaiting parity bit
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; - 3: awaiting stop bit
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; it reaches 11, we know we're finished with the frame.
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; R19: Register used for parity computations
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; R19: Register used for parity computations and tmp value in some other places
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; R20: data being sent to the 595
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; Y: pointer to the memory location where the next scan code from ps/2 will be
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; written.
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@ -174,14 +174,13 @@ loop:
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; Process the data bit received in INT0 handler.
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processbit:
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in r16, GPIOR0 ; backup GPIOR0 before we reset T
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andi r16, 0x1 ; only keep the first flag
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in r19, GPIOR0 ; backup GPIOR0 before we reset T
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andi r19, 0x1 ; only keep the first flag
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cbi GPIOR0, 0
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clt ; ready to receive another bit
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; We've received a bit. reset timer
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ldi r19, TIMER_INITVAL
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out TCNT0, r19
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rcall resetTimer
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; Which step are we at?
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tst r18
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@ -193,7 +192,7 @@ processbit:
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; step 3: stop bit
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clr r18 ; happens in all cases
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; DATA has to be set
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tst r16 ; Was DATA set?
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tst r19 ; Was DATA set?
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breq loop ; not set? error, don't push to buffer
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; push r17 to the buffer
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st Y+, r17
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@ -203,7 +202,7 @@ processbit:
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processbits0:
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; step 0 - start bit
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; DATA has to be cleared
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tst r16 ; Was DATA set?
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tst r19 ; Was DATA set?
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brne loop ; Set? error. no need to do anything. keep r18
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; as-is.
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; DATA is cleared. prepare r17 and r18 for step 1
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@ -216,7 +215,7 @@ processbits1:
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; We're about to rotate the carry flag into r17. Let's set it first
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; depending on whether DATA is set.
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clc
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sbrc r16, 0 ; skip if DATA cleared.
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sbrc r19, 0 ; skip if DATA cleared.
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sec
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; Carry flag is set
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ror r17
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@ -228,21 +227,23 @@ processbits1:
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rjmp loop
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processbits2:
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; step 2 - parity bit
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mov r1, r16
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mov r1, r19
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mov r19, r17
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rcall checkParity ; --> r16
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cp r1, r16
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; TODO: implement "resend requests" on parity check failure
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brne processbitReset ; r1 != r16? wrong parity
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brne processbitError ; r1 != r16? wrong parity
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inc r18
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rjmp loop
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processbitError:
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clr r18
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ldi r19, 0xfe
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rcall sendToPS2
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rjmp loop
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processbitReset:
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clr r18
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ldi r16, TIMER_INITVAL
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out TCNT0, r16
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ldi r16, (1<<TOV0)
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out TIFR, r16
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rcall resetTimer
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rjmp loop
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; send next scan code in buffer to 595, MSB.
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@ -293,6 +294,105 @@ sendTo595Loop:
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rjmp loop
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resetTimer:
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ldi r16, TIMER_INITVAL
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out TCNT0, r16
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ldi r16, (1<<TOV0)
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out TIFR, r16
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ret
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; Send the value of r19 to the PS/2 keyboard
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sendToPS2:
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; We don't use the general INT0 mechanism here. However, we still want
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; to listen to PCINT, so we don't disable interrupts entirely, just
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; INT0.
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ldi r16, (1<<PCIE)
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out GIMSK, r16
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; First, indicate our request to send by holding both Clock low for
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; 100us, then pull Data low
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; lines low for 100us.
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cbi PORTB, CLK
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sbi DDRB, CLK
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rcall resetTimer
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; Wait until the timer overflows
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in r16, TIFR
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sbrs r16, TOV0
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rjmp PC-2
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; Good, 100us passed.
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; Pull Data low, that's our start bit.
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cbi PORTB, DATA
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sbi DDRB, DATA
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; Now, let's release the clock. At the next raising edge, we'll be
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; expected to have set up our first bit (LSB). We set up when CLK is
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; low.
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cbi DDRB, CLK ; Should be starting high now.
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; We will do the next loop 8 times
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ldi r16, 8
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; Let's remember initial r19 for parity
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mov r1, r19
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sendToPS2Loop:
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; set up DATA
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cbi PORTB, DATA
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sbrc r19, 0 ; skip if LSB is clear
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sbi PORTB, DATA
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lsr r19
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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dec r16
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brne sendToPS2Loop ; not zero? loop
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; Data was sent, CLK is high. Let's send parity
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mov r19, r1 ; recall saved value
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rcall checkParity ; --> r16
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; set parity bit
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cbi PORTB, DATA
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sbrc r16, 0 ; parity bit in r16
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sbi PORTB, DATA
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; Wait for CLK to go high
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sbis PINB, CLK
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rjmp PC-1
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; We can now release the DATA line
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cbi DDRB, DATA
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; Wait for DATA to go low. That's our ACK
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sbic PINB, DATA
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rjmp PC-1
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; Wait for CLK to go low
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sbic PINB, CLK
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rjmp PC-1
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; We're finished! Enable INT0, reset timer, everything back to normal!
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rcall resetTimer
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clt ; also, make sure T isn't mistakely set.
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ldi r16, (1<<INT0)|(1<<PCIE)
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out GIMSK, r16
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ret
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; Check that Y is within bounds, reset to SRAM_START if not.
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checkBoundsY:
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tst YL
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